A parameter extraction method using cutoff measurement for alarge-scale HSPICE model of HBT's

We present an accurate parameter extraction method for the HBT large-signal equivalent circuit model in which several extrinsic parasitics are connected to HSPICE BJT model. The measured Gummel plot are used to extract DC model parameters of HBT using HSPICE. Capacitances are then obtained from S-parameter measurements of the HBTs biased to cutoff. The other parameters are determined from the active device S-parameters. The large-signal modeled Gummel plot and S-parameters show good agreement with the measured ones, respectively     

An efficient analytical approach for extracting the emitter inductance of collector-up HBTs

An efficient analytical parameter-extraction approach for the emitter inductance in a hybrid-/spl pi/ equivalent circuit of collector-up heterojunction bipolar transistors (HBTs) is developed for the first time. A full set of elements is derived unambiguously from impedance and admittance formulation. The good agreement between measured and simulated S-parameters ensures the accuracy of this method.     

An analytic method to determine GaAs FET parasitic inductances anddrain resistance under active bias conditions

An analytic technique to determine the parasitic inductances, source resistance, and drain resistance of the FET equivalent circuit is presented in this paper. The method exploits the frequency dependence of the extracted circuit parameters to determine the parasitic inductances and drain resistance from S-parameters measured over frequency for one active bias condition. Given a value for the parasitic gate resistance R _g, all of the other equivalent-circuit parameters are uniquely extracted. The method is fast and robust, making it suitable for in-line statistical process tracking, as well as device modeling. A process tracking example for a 12-wafer 1864-device sample and FET modeling results up to 40 GHz are also presented     

Direct parameter-extraction method for HBT small-signal model

An accurate and broadband method for the direct extraction of heterojunction bipolar transistor (HBT) small-signal model parameters is presented in this paper. This method differs from previous ones by extracting the equivalent-circuit parameters without using special test structures or global numerical optimization techniques. The main advantage of this method is that a unique and physically meaningful set of intrinsic parameters is extracted from the measured S-parameters for the whole frequency range of operation. The extraction procedure uses a set of closed-form expressions derived without any approximation. An equivalent circuit for the HBT under a forward-bias condition is proposed for extraction of access resistances and parasitic inductances. An experimental validation on a GaInP/GaAs HBT device with a 2×25 μm emitter was carried out, and excellent results were obtained up to 30 GHz. The calculated data-fitting residual error for three different bias points over 1-30 GHz was less then 2%     

Analytical parameter extraction of the HBT equivalent circuit withT-like topology from measured S-parameters

A pure analytical method for extraction of the small-signal equivalent circuit parameters from measured data is presented and successfully applied to heterojunction bipolar transistors (HBT's). The T-like equivalent circuit is cut into three shells accounting for the connection, and the extrinsic and intrinsic parts of the transistor. The equivalent circuit elements are evaluated in a straightforward manner from impedance and admittance representation of the measured S-parameters. The measured data are stripped during the extraction process yielding, step by step, a full set of circuit elements without using fit methods. No additional knowledge of the transistor is needed to start the extraction process with its self-consistent iteration loop for the connection shell. The extrinsic and intrinsic equivalent circuit elements are evaluated using their bias and frequency dependencies. This method yields a deviation of less then 4% between measured and modeled S-parameters     

An approach for SiGe HBT small-signal modelling up to 40 GHz

In this article, a simple method for the small-signal equivalent-circuit modelling of SiGe heterojunction bipolar transistors (HBTs) fabricated with a 0.13-μm BiCMOS technology is proposed. The presented transistor model is compatible with BiCMOS processes and takes into account the parasitic effects such as substrate effect and the extrinsic capacitances. The parameter-extraction approach is based on the analytically derived equations in conjunction with the optimisation technology. The intrinsic parameters are described as the function of extrinsic resistances. The extrinsic resistances are iteratively extracted by the variance of the intrinsic elements as an optimisation criterion. The proposed modelling approach is validated by SiGe HBTs with 0.2 × 5.9 μm² emitter occupying area from 50 MHz to 40 GHz. The agreements between the measured and modelled data are excellent in the desired frequency range over a wide range of bias points with different bias conditions.     

A peeling algorithm for extraction of the HBT small-signal equivalent circuit

Direct extraction is the most accurate method for the determination of equivalent-circuits of heterojunction bipolar transistors (HBTs). The method is based on first determining the parasitic elements and then the intrinsic elements analytically. The accuracy and robustness of the whole algorithm therefore is determined by the quality of the extraction of the extrinsic elements. This paper focuses on a new extraction method for the extrinsic capacitances which have proven to be the main source of uncertainty compared to the other extrinsic parameters. Concerning the intrinsic parameters, all the elements are extracted using exact closed-form equations, including exact expressions for the base-collector capacitances, which model the distributed nature of the base. The expressions for the base-collector capacitances are valid for both the hybrid-/spl pi/ and the physics-based T-topology equivalent circuits. Extraction results for InP HBT devices on measured S-parameters up to 100 GHz demonstrate good modeling accuracy.     

Very high-frequency small-signal equivalent circuit for shortgate-length InP HEMTs

A small-signal equivalent circuit for short gate-length InP high electron-mobility transistors (HEMTs) operating at very high frequency (HF) is proposed. First, the extrinsic parameters of the equivalent circuit are determined using a cold HEMT, but without forward gate bias. Then the intrinsic parameters of the equivalent circuit are extracted, including the frequency dependence of some of them. A fast and accurate method based on least-squares regressions is presented to obtain the extrinsic and intrinsic parameters from measured S-parameters. The improved equivalent circuit accurately fits the S-parameters of 0.25-μm InP HEMTs over the 500-MHz up to 40-GHz measurement bandwidth, for all gate-to-source and drain-to-source voltages     

SiGe HBT非准静态小信号等效电路的参数提取

提出了一种硅锗异质结双极型晶体管（SiGe HBT）非准静态效应的小信号等效电路模型的参数提取方法。整个参数提取过程建立在由非准态效应的小信号等效电路推导出的一系列泰勒级数解析公式并结合参数直接法,该方法依赖于测量的S参数,不使用任何的数值优化法,参数提取结果使用CAD仿真验证。结果表明该参数提取方法简单易行,较为精确,该方法能够用到不同工艺SiGe HBT参数提取。     

MEXTRAM model based SiGe HBT large-signal modeling

An improved large-signal equivalent-circuit model for SiGe HBTs based on the MEXTRAM model (level 504.5) is proposed. The proposed model takes into account the soft knee effect. The model keeps the main features of the MEXTRAM model even though some simplifications have been made in the equivalent circuit topology. This model is validated in DC and AC analyses for SiGe HBTs fabricated with 0.35-μm BiCMOS technology, 1×8μm2emitter area. Good agreement is achieved between the measured and modeled results for DC and S-parameters (from 50 MHz to 20 GHz), which shows that the proposed model is accurate and reliable. The model has been implemented in Vefilog-A using the ADS circuit simulator.     

HBT小信号等效电路参数解析提取

提出一种求解异质结双极晶体管(HBT)小信号等效电路模型的解析方法。在提取过程中,采用集电极开路测量和直流测量相结合的方法,精确提取到了具有物理意义的唯一的外部串联电阻值,并在精确提取非本征参数的基础上,直接提取本征参数。较大频率范围S参数的计算值与测量值有很好的吻合。     

An Improved Small-Signal Parameter-Extraction Algorithm for GaN HEMT Devices

A highly efficient and accurate extraction algorithm for the small-signal equivalent-circuit parameters of a GaN high electron-mobility transistor device is presented. Elements of the extrinsic equivalent-circuit topology are evaluated using a modified “cold field-effect transistor” approach whereby the undesirable need to forward bias the device's gate terminal is avoided. Intrinsic elements are determined based on a circuit topology, which identifies, for the first time, a time delay in the output conductance of GaN-based devices. The validity of the proposed algorithm has been thoroughly verified with excellent correlation between the measured and modeled $S$-parameters up to 50 GHz.      

A new pinched-off cold-FET method to determine parasiticcapacitances of FET equivalent circuits

A new pinched-off cold FET method to extract the parasitic capacitances of FETs is proposed in this paper. The method is based on a physically meaningful depletion-layer model and the theoretical analysis of the two-port network for the pinched-off cold FETs. The parasitic gate capacitance (C_pg) and the parasitic drain capacitance (C _pd) of FETs are extracted using the linear regression technique associated with the frequency responses of Y-parameters. The extraction method can be applied to the small-signal equivalent-circuit modeling of the FETs including MESFETs, heterojunction FETs, and high-electron-mobility transistors. According to the new analytical method, the simulated S-parameters exhibit great agreement with the measured S-parameters for the equivalent-circuit models of FETs     

Direct parameter extraction of SiGe HBTs for the VBIC bipolar compact model

An improved direct parameter extraction method of SiGe heterojunction bipolar transistors (HBTs) for the vertical bipolar intercompany (VBIC)-type hybrid-/spl pi/ model is developed. All the equivalent circuit elements are extracted analytically from S-parameter data only and without any numerical optimization. The proposed technique of the parameter extraction, differing from the previous ones, focuses on correcting the pad de-embedding error for an accurate and invariant extraction of intrinsic base resistance (R/sub bi/), formulating a new parasitic substrate network, and improving the extraction procedure of transconductance (g/sub m/), dynamic base-emitter resistance (r/sub /spl pi//), and base-emitter capacitance (C/sub /spl pi//) using the accurately extracted R/sub bi/. The extracted parameters are frequency-independent and reliable due to elimination of any de-embedding errors. The agreements between the measured and model-calculated data are excellent in the frequency range of 0.2-10.2 GHz over a wide range of bias points. Therefore, we believe that the proposed extraction method is a simple and reliable routine applicable to the optimization of transistor design, process control, and the improvement of VBIC compact model, especially for SiGe HBTs.     

Harmonic and two-tone intermodulation distortion analyses of theinverted InGa/InAlAs/InP HBT

Harmonic and two-tone intermodulation distortion analyses of the InGaAs/InAlAs/InP collector-up heterojunction bipolar transistor (HBT) are performed by a simple Ebers-Moll model. The parasitic elements of the equivalent circuit are extracted at zero bias by numerical optimization. A semianalytical approach is used to extract the intrinsic parameters of the small-signal equivalent circuit at nonzero bias points. Appropriate equations given by device physics are fitted to the bias variation of intrinsic parameters so that the Ebers-Moll model parameters can be extracted. Agreement between simulation and measurement of harmonic and intermodulation distortion is achieved     

Parameter extraction technique for HBT equivalent circuit usingcutoff mode measurement

A parameter extraction method based on the S-parameter measurements of the heterojunction bipolar transistors (HBTs) biased to cutoff is proposed. This method is applied to confirm the results for the RF probe pad and interconnection pattern parasitics obtained from the special test structures, and to determine some of the device capacitances of the HBT. The remaining device parameters are extracted by the S-parameter measurements of the devices biased to the active mode. The extraction technique gives good agreement between the equivalent circuit and the measured S-parameters of the HBT including probe pads and interconnections     

Experimental equivalent-circuit modeling of SMD inductors forprinted circuit applications

An understanding of the high-frequency parasitic and packaging effects of passive surface-mounted devices (SMDs) can be gained from equivalent-circuit characterization of the device. We develop a circuit model which accurately characterizes the nonideal behavior of SMD inductors mounted on a printed circuit board (PCB), considering the device packaging and the interaction between board layout and component parasitics. The model is valid over a wide frequency band up to the first resonance of the inductor. The equivalent-circuit parameters are extracted in closed form from an accurate measurement of the S-parameters of the board-mounted SMD inductor, without the necessity for cumbersome optimization procedures normally followed in RF circuit synthesis. This procedure of measuring the component in its designed PCB environment is referred to as extrinsic characterization, in contrast to the conventional intrinsic characterization employed in RF bridges and LCR meters, which does not include the board layout effects. The developed closed-form model can be directly incorporated in commercial CAD packages, and thus, it simplifies the analysis of electromagnetic field behavior in PCBs, such as prediction of radiated emissions, signal integrity, and EMI     

SiGe HBT小信号等效电路的参数直接提取

提出了一种求解硅锗异质结双极型晶体管(SiGe HBT)小信号等效电路模型的参数直接提取方法.整个提取过程使用由小信号等效电路推导出的一系列解析表达式,不使用任何数值优化方法.参数提取结果使用ADS软件仿真验证.结果表明,该方法简单易行,较为精确.     

Small-signal model parameter extraction of E-mode N-polar GaN MOS-HEMT using optimization algorithms and its comparison

An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed,which is a combination of a conventional analytical method and optimization techniques.The extrinsic parameters such as parasitic capacitance,inductance and resistance are extracted under the pinch-off condition.The intrinsic parameters of the small-signal equivalent circuit (SSEC) have been extracted including gate forward and backward conductance.Different optimization algorithms such as PSO,Quasi Newton and Firefly optimization algorithm is applied to the extracted parameters to minimize the error between modeled and measured S-parameters.The different optimized SSEC models have been validated by comparing the S-parameters and unity current-gain with TCAD simulations and available experimental data from the literature.It is observed that the Firefly algorithm based optimization approach accurately extracts the small-signal model parameters as compared to other optimization algorithm techniques with a minimum error percentage of 1.3％.