考虑温度分布效应的RLC互连延时分析

基于等效Elmore延时模型和分段分布参数思想提出了一种RLC互连延时解析模型,该模型同时考虑了瓦连线温度分布效应和电感效应对延时的影响,更加贴近实际情况,在实际应用中具有重要意义.仿真结果表明,对于简单的RLC互连树形结构而言,所提模型的延时误差在10%以内,且仿真效率高.     

热效应致RLC互连延时变化研究

针对热效应导致RLC互连延时增加的现象进行了研究.提出了一种温度依赖的RLC互连延时模型.该模型可以用以量化热效应对互连延时的影响.仿真结果显示,对于RLC互连,温度每增加20℃,延时将会增加5%-6%.     

考虑工艺波动影响的RLC互连统计延时

该文提出了一种考虑工艺波动的统计RLC互连延时分析方法。文中首先给出了考虑工艺波动的寄生参数和矩的构建方法,然后基于Weibull分布给出了RLC互连的统计延时模型。所提方法同样适用于已有的延时模型如Elmore模型,等效Elmore模型和D2M模型。通过对几种模型的比较,表明,基于Weibull分布的RLC互连的统计延时模型是最精确的,和HSPICE相比,50%延时误差最大0.11%,蒙特卡洛分析中的均值和平均偏差误差最大2.02%。     

基于工艺波动下的互连延时统计模型

为了有效分析工艺波动对互连性能的影响,本文基于对数正态分布函数提出了一种RLC互连延时统计模型。在给定互连参数波动范围条件下,首先得到了电路矩的表达式,然后推导出了RLC互连延时均值和标准差。针对65nm和45nm的RLC互连树进行了验证,和HSPICE相比,采用本文方法计算得到的互连延时均值和标准差误差分别低于1%和5%。仿真表明本文方法具有足够的效率和精度。     

一种稳定的RLC互连π模型构建及其应用

基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型,并讨论了它在互连树延时和逻辑门延时估计中的应用.结果表明,该模型与已有方法相比精度有一定程度的提高.     

一种考虑温度时间-空间分布的解析互连延时模型

本文从热扩散方程出发,得到了互连温度时间-空间分布的解析表达式.考虑互连温度对互连电阻和Elmore延时的影响,同时提出了一种用以分析互连时间-空间温度分布效应对互连延时影响的等效内阻模型.基于所提出的模型,详细地分析了互连长度、输入信号频率和功率对互连延时的影响.所提出的互连温度分布和延时解析模型可以应用于深亚微米温度相关的互连性能分析中.     

考虑工艺波动的RLC互连延时统计模型

基于概率解释算法的原理,提出了一种考虑工艺波动的RLC互连延时统计模型,该模型使用了对数正态分布函数。在给定互连参数波动范围条件下,利用该算法计算延时仅需要采用前两个瞬态。和HSPICE相比,Monte Carlo分析中的均值和平均偏差误差分别低于0.7％和0.51％。模型计算简单且精度高,可以满足互连线仿真要求。     

一种稳定的RLC互连Π模型构建及其应用

基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型，并讨论了它在互连树延时和逻辑门延时估计中的应用．结果表明，该模型与已有方法相比精度有一定程度的提高．     

驱动复杂RLC互连树的逻辑门延时

提出了一个用于估计RLC互连树驱动点导纳的闭端等效π模型,并将其用于驱动复杂RLC互连树的逻辑门延时的估计中.与其他方法相比,它具有结构简单、精度较高的特点.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

High speed interconnect data dependent jitter analysis

This paper focuses on modeling and characterizing the data dependent jitter (DDJ) in high-speed interconnect. The analysis process is performed based on the Fourier series using the interconnect RLC model. By calculating the pattern dependent delay deviations, the DDJ is characterized. To validate the model accuracy, the analysis results have been compared against Cadence simulations. The interconnect layout optimization is also explored to minimize the DDJ.     

基于RLC模型的树形互连线时延估算

文章给出了基于RLC模型的树形互连线50％时延的估算公式。这里给出的算法精度较高(与SPICE仿真结果的误差在10％以内)，而且具有与Elmore时延相同的算法复杂度。该算法基于RLC模型，可以得到各种不同的阻尼响应，包括欠阻尼振荡，而Elmore时延只能反应呈单调变化的过阻尼响应。因此，该算法对阻尼响应的估算精度高于Elmore时延，而其相当的计算开销(算法复杂度)使它可以应用于Elmore时延使用的各个领域。     

A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect

Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.     

一种基于Birnbaum-Saunders分布的新型互连时延统计模型

基于统计概率分布的互连时延模型具有效率高、准确性好的特点,但此类方法往往包含一些查表运算.本文提出了一种基于Birnbaum-Saunders分布的互连线时延模型,避免了查表运算,且仅需要采用前两个瞬态,计算简单,准确性较好,并提出了一种精度修正算法,使该方法具有更好的适应性.