共查询到16条相似文献,搜索用时 93 毫秒
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基于概率解释算法的原理,提出了一种考虑工艺波动的RLC互连延时统计模型,该模型使用了对数正态分布函数。在给定互连参数波动范围条件下,利用该算法计算延时仅需要采用前两个瞬态。和HSPICE相比,Monte Carlo分析中的均值和平均偏差误差分别低于0.7%和0.51%。模型计算简单且精度高,可以满足互连线仿真要求。 相似文献
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Ismail Y.I. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(2):195-206
A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale 相似文献
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El-Moursy M.A. Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(3):396-400
Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE. 相似文献
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This paper focuses on modeling and characterizing the data dependent jitter (DDJ) in high-speed interconnect. The analysis process is performed based on the Fourier series using the interconnect RLC model. By calculating the pattern dependent delay deviations, the DDJ is characterized. To validate the model accuracy, the analysis results have been compared against Cadence simulations. The interconnect layout optimization is also explored to minimize the DDJ. 相似文献
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Azadpour M.A. Kalkur T.S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(6):1143-1146
Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths. 相似文献