A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

A charge-domain quadrature sampling circuit realization in 0.35 /spl mu/m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply.     

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW

A bandpass modulator with two time-interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40 MHz IF provide a signal band of 1 MHz with 72 DR and 65.1 dB peak SNR. The circuit, integrated in a 0.18 CMOS technology, uses a 60 MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 . The power consumption is 16 mW with 1.8 V supply.     

一种数字式微波延迟线设计

通过混频将微波信号下变频到中频,在中频进行数字化,并采用循环存取法完成数字信号延迟处理,最后再将数字信号还原成模拟信号并上变频回与输入信号频率相同的微波频段,最终设计出频率4 300MHz、带宽70MHz、最大延迟时间50μs、延迟步进5ns的微波频段延迟线,该产品有很好的直通及三次信号抑制性能。     

A high-performance monolithic IF amplifier incorporating electronic gain control

A direct-coupled monolithic IF amplifier that incorporates an active gain control stage and exhibits a power gain of 50 dB and an AGC range of 60 dB at 50 MHz is described. This circuit has negligible change in either input or output admittance, and has excellent signal linearity over the full range of gain control. Experimental and theoretical analyses are made of the large signal response, stability, available gain, and noise behavior of the circuit. An application to color television is discussed in which the functions of the 45-MHz IF amplifier and the dc-AGC circuitry are fabricated on a single die.     

A 20 GHz microwave sampler

A microwave sampler circuit which operates over the frequency band of 1-20 GHz and has a number of novel features is described. These features include a wideband microstrip-to-slot balun and a wideband active isolator the function of which is to reduce the local oscillator to RF leakage from the input port of the sampler. The signal-to-noise ratio over the input bandwidth is greater than 20 dB at an input power level of -32 dBm. This signal-to-noise ratio was measured in an IF bandwidth of 175 MHz and includes the contribution from the IF amplifier. The sampler, which is made on alumina using MIC techniques, has an integrated impulse generator driven with a sinusoidal local oscillator of only 20 dBm over the frequency band of 250-350 MHz. The IF signal is in the 10-175-MHz band. The RF input VSWR is better than 2:1 up to 20 GHz, and the oscillator to RF breakthrough is better than -58 dBm (-78 dBc) when driven with a local oscillator of 20 dBm. This unusually low leakage was achieved by using the active isolator prior to the sampling circuit     

A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule

A novel automatic-gain-control (AGC) architecture utilizing wideband current feedback is proposed for the baseband circuit of a wireless endoscope capsule. The baseband circuit consists of a fast-settling wideband AGC loop and an amplitude-shift-keying demodulator. Additional integrators in the reverse signal path provide negative feedback, bandpass-filtering effect, attenuating low-frequency noises, and dc offset from the radio-frequency front end. The baseband circuit fabricated in a 180-nm complementary metal-oxide-semiconductor process achieves a wide-intermediate-frequency (IF) carrier frequency in the range of 0.5-40 MHz, a measured settling time of 2 mus, and an input sensitivity of -57 dBm. The entire baseband demodulator dissipates only 5 mA, with a 1.8-V supply at a data rate of 1.37 Mb/s and an IF carrier frequency of 10 MHz.     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35$muhbox m$BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whose results were verified on silicon. The measured silicon results indicate the highest published IF sampling performance to date and prove the viability of the “SHA-less” architecture for IF/RF sampling ADCs. The ADC is calibration-free and achieves a DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is 75 dB below Nyquist, and stays above 71 dB up to 500 MHz. The low-frequency SFDR is about 100 dB, and stays above 90 dB up to about 300 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a total RMS jitter of only 50 fs.     

A Common Source Input Cross Coupled Quad CMOS Mixer*

A CMOS doubly balanced mixer circuit is implemented with a source follower input and a cross coupled mixing quad. The circuit employs an all N-channel configuration and is suitable for high frequency applications. As a down-converter with an RF input of 2.0 GHz and an IF output of 200 MHz, the mixer demonstrates 9 dB of conversion loss with a corresponding input referred third order intercept of 0 dBm. As an up-converter with an IF input frequency of 400 MHz and an RF output of 2.4 GHz, the mixer demonstrates 14 dB of conversion loss.     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

MMIC compatible lightwave-microwave mixing technique

The work presented here concerns the mixing of a microwave signal with a modulated optical signal in a MESFET. A brief theoretical analysis of the mixing mechanism is given in terms of the input signal parameters and device characteristics. Experimental results for the IF response of the MESFET as a function of RF frequency, incident optical power, optical modulation depth and gate bias voltage are shown. The IF response and the noise figure of the MESFET below 700 MHz were smaller than those of a p-i-n detector/Schottky mixer combination     

20GHz镜频抑制谐波混频器

镜频抑制混频器能有效地抑制镜像频率,提高雷达和通信系统的抗干扰能力。介绍了一个20 GHz二次谐波镜频抑制混频器的设计与制作,该镜频抑制混频器采用两个相同的二次谐波混频器做为两路混频单元,两路射频输入和中频输出分别用90°的功分器/合路器与两路混频器相连,本征用威尔金森功分器等幅同相输入两路混频。借助于90°的功分器,两路混频器的镜频产物在中频90°合路器的输出端口反相抵消,有用中频在90°合路器的输出端口同相叠加。利用ADS和HFSS对该混频器进行了仿真设计,并对实际电路进行了加工测试。经测试,当中频固定在400 MHz时,射频在20～21 GHz内变频损耗小于10 dB,镜频抑制大于20 dB。     

0.1 THz鳍线单平衡式基波混频电路研究

研究了一种基于石英基片的0.1 THz频段的鳍线单平衡混频电路,混频电路的射频和本振信号分别从WR10标准波导端口通过波导单面鳍线微带过渡和波导微带探针过渡输入,中频信号通过本振中频双工器输出。这是一种新型的混频电路形式,与传统的W波段混频器相比,混频电路可以省略一个复杂的W波段滤波器,具有电路设计简单、安装方便的特点。该电路使用两只肖特基二极管通过倒装焊工艺粘结在厚度为75 m的石英基片上,石英基片相对传统基板,可以极大提高电路加工精度。在固定50 MHz中频信号时,射频90~110 GHz范围内,0.1 THz混频器单边带变频损耗小于9 dB。     

A 0.5–7.5 GHz Ultra Low-Voltage Low-Power Mixer Using Bulk-Injection Method by 0.18- μm CMOS Technology

A fully differential low-voltage low-power downconversion mixer using a TSMC 0.18-mum CMOS logic process is presented in this letter. The mixer was designed with a four-terminal MOS transistor, the radio-frequency (RF) and local-oscillator signals apply to the gate and bulk of the device, respectively while the intermediate frequency (IF) signals output was from the drain. The mixer features a maximum conversion gain of 5.7dB at 2.4 GHz, an ultra low dc power consumption of 0.48 mW, a noise figure of 15 dB, and an input IP of 5.7 dBm. Moreover, the chip area of the mixer core is only 0.18 times 0.2 mm². The measured 3-dB RF frequency bandwidth is from 0.5 to 7.5 GHz with an IF of 100 MHz, and it is greatly suitable for low-power in wireless communication.     

一种双耦合双混频中频信号功率反馈电路

在自动电平控制系统中,常用功率反馈电路存在一个主要限制:调幅动态范围受限于电平检波器和相关电路,使其远远低于线性调制器的功率可变范围。文中介绍了一种双耦合双混频中频信号功率反馈电路,使检波器只需检测固定中频信号的功率大小即可反馈调节射频输出信号的功率幅度。经测试,电路射频输入信号在24 GHz变化时,得到的中频信号频率固定不变,等于晶振信号54 MHz。线性调制器的衰减量在031.5 dB变化时,中频信号功率与射频输出信号功率成良好的线性关系,满足预期的设计要求。     

A synchronous phase-lock loop detector for integrated AM radio

A synchronous phase-lock loop AM detector has been realized on a single chip in a bipolar process with an f/SUB T/ of 400 MHz. The circuit accepts input signals at an IF frequency of 450-500 kHz with effective values between 20 and 100 mV. The phase-lock loop capture range is about 150 kHz. AM signals with over 80% modulation depth can be demodulated with less than 1% harmonic distortion in the audio output signal. The power dissipation of the chip is 120 mW at 8 V. The total chip size is 1900/spl times/1300 /spl mu/m/SUP 2/. Since the VCO and the 90/spl deg/ phase shift are completely realized on-chip, large signals at the IF frequency do not occur at the pins of the IC, and parasitic feedback of such signals to the IF amplifier input is minimized.     

雷达中频放大器的线性对数双特性设计

雷达数字中频接收机需要一个线性中频预放大电路和一个监测用的对数中频放大器。采用射频变压器形成输入匹配网络,采用高性能低噪声宽带差分放大器AD8350作为线性放大器件,采用双调谐回路作为选频网络,采用魔T电路构成功率分配网络,采用高动态范围宽带对数放大器AD8309作为对数放大器件,设计了一个兼具线性和对数特性的中频放大器。实验表明,该放大器中频输入输出阻抗50Ω,中心频率30 MHz,带宽4 MHz。线性通道增益为18 dB,输出动态范围达98 dB(1 dB压缩点-90 dBm和+8 dBm)。对数通道中,在输入功率为-68 dBm～-8 dBm时,对数放大器输出电压范围对应为0.19 V～2.06 V。     

基于93000 ATE的高速高分辨率ADC动态参数测试

基于Verigy 93000 ATE,采用外挂高性能晶振和射频信号源的测试方案,实现了11位分辨率AD80141最高400 MHz输入信号的测试。结果表明,输入信号为140 MHz以下时,SNR测试值与目标值相差不到1 dB;输入信号为300 MHz、400 MHz时,SNR测试值分别达到59.46dB和57.03 dB。