GLONASS卫星信号误差特性的观测与分析

首先阐述了GLONASS卫星信号体制的特点，然后根据大量的在GPS/GLONASS接收机中观测的GLONASS卫星信号的测量数据，分析了GLONASS卫星信号的误差特性，以及与GPS卫星的差异。     

GLONASS卫星信号仿真器设计与实现

基于DSP+FPGA的设计方案,实现了多通道GLONASS卫星信号的硬件仿真器。简单给出了硬件系统的基本架构,重点叙述了基于此上的软件结构和程序流程,并通过实验验证了该方案的可行性。实验结果表明,本方案设计的GLONASS仿真器信号逼真度高、可编程性强、使用灵活,并具有一定的动态性能,为GLONASS接收机的性能检测提供了有益的支持。     

双模导航接收机时间系统一致性研究

卫星导航接收机在某些特殊地域使用时,集成了GPS和GLONASS的双模接收机可以弥补单模接收机的劣势,从而明显提高定位的可靠性及可用性。而GPS和GLONASS时间系统的不一致性对GPS/GLONASS双模接收机有重要制约,对其定位精度产生了一定影响。对GPS和GLONASS的时间系统差异进行了研究,给出对其一致性分析的具体方法。可推广至多导航模块的接收机中,从而使定位精度更加精准可靠。     

多模卫星信号仿真器上位机软件设计与实现

运用面向对象和多线程的技术,在VC++6.0环境下对GPS/GLONASS/BD1三模卫星信号仿真器上位机软件进行了设计与开发,重点分析并完成了多导航系统时空统一、导航电文生成、卫星与用户的伪距仿真和用户轨迹计算等功能模块,实现了统一时基模式下三模卫星信号的高逼真仿真.商业接收机的实验结果表明,该仿真软件操控灵活,与下位机连接合成的信号逼真度高,为各类接收机的性能检测提供了有益支持.     

多模卫星信号仿真器上位机软件设计与实现

运用面向对象和多线程的技术,在VC＋＋6．0环境下对GPS／GLONASS／BD1三模卫星信号仿真器上位机软件进行了设计与开发,重点分析并完成了多导航系统时空统一、导航电文生成、卫星与用户的伪距仿真和用户轨迹计算等功能模块,实现了统一时基模式下三模卫星信号的高逼真仿真。商业接收机的实验结果表明,该仿真软件操控灵活,与下位机连接合成的信号逼真度高,为各类接收机的性能检测提供了有益支持。     

新产品：东方联星公司多模兼容芯片抱眼年会

受大会邀请,东方联星公司张峻林总经理对“多模兼容芯片技术”作了特别报告。报告充分向大家展示了该公司已经批量生产和应用的北斗多模卫星导航芯片,以该款芯片为核心的卫星导航接收机,可以同时接收北斗二号、GPS、GLONASS卫星信号,具有北斗、GPS或GLONASS单星座定位、北斗／GPS双星座联合定位、北斗／GLONASS双星座联合定位、北斗／GPS／GLONASS三星座联合定位的能力。     

卫星导航信号模拟器体系结构分析

卫星导航信号模拟器是一种高精度的标准信号源,可以产生卫星导航信号(GPS、GLONASS、Galileo等),为导航接收机的研制开发、测试提供仿真环境。分类介绍了当前世界上主要的卫星导航信号模拟器产品,并对其体系结构进行了分析。     

GLONASS C/A码接收机研制总体方案设计

根据我们开发GPS接收机的基础与经验,提出用GP芯片组实现GLONASS接收机的方案。这种实现节省了开发的费用,缩小了体积。本文论述了如何利用GP芯片组实现GLONASS接收机,以及对基于这种思想的多种方案进行了比较,提出了切实可行的具体实现方案。     

基于LT1568的高频段有源滤波器的设计

对于高频信号,传统的由分立元件搭建的LC无源滤波网络,设计过程复杂,对信号衰减较大。为了简化高频段滤波器的设计过程、提高滤波效率,提出了使用低噪声高频有源RC滤波芯片LT1568来设计高频滤波电路,介绍其性能,分析了其工作原理。并以高频多普勒接收机内部带通滤波器设计为例,介绍滤波电路的设计方法。实验仿真表明用其搭建的高频有源滤波电路滤波效果明显、电路简单、方便易用。     

卫星导航兼容机的需求

以GPS／GLONASS卫星导航兼容接收机为代表开拓了一片小小的市场空间，由于其价格比普通的GPS接收机昂贵许多．所以它的用户面较窄。国际上，真正有政策规定的只有俄罗斯，明令凡进口卫星导航接收机者必须是GPS／GLONASS兼容机，不允许进单一的GPS接收机，这当然是出于为了让自己的GLONASS卫星能用起来     

一种用于电视无源双基地雷达系统中的射频接收系统

主要介绍了一种低噪声大动态接收机的设计。该机用于电视无源双基地雷达系统中，接收参考信号直达波。该接收机采用了自行设计的低噪声射频放大器，降低了接收机的整机噪声系数，使用了AGC（自动增益控制）结构，大大提高了接收信号的范围。因此采用低噪声大动态接收机可以提高接收信号的灵敏度和信噪比，使得系统信号处理的准确度大大提高。     

A Single Chip 160 Mbit/s Cable Communication Circuit Including a Gain Controlled Equalizer and a Data Regenerating PFLL

In this paper a single chip transmitter and receiver interface circuit for 160 Mbit/s CMI-coded data transmission is presented. The receiver circuit includes a 12 dB cable equalizer to compensate for nonconstant cable attenuations. There is also a PFLL for data regeneration and to extract a 320 MHz oscillator clock signal. The frequency characteristics of the equalizer are controlled with an automatic gain control loop (AGC). The PFLL is a combination of two separate control loops, the purpose of which is to keep the integrated oscillator on the narrow locking range of the data loop. The frequency loop has been designed with a frequency detector to avoid interferences between the two control loops. The transmitter includes a cable driver supplying a stable 1 Vpp signal amplitude to the transmission line and also a PLL to extract a 320 MHz clock signal.     

Wireless communication in a flip-chip package using integrated antennas on silicon substrates

An intrachip wireless interconnect using integrated antennas is demonstrated in a flip-chip ball grid array package. The wireless interconnect consists of a transmitter-receiver pair, which is fabricated in a 0.18-/spl mu/m CMOS process. A 15-GHz signal is generated and broadcasted across the integrated circuit. The signal is picked up by a receiver 4 mm away on the same integrated circuit and frequency divided by eight to produce a 1.875-GHz local clock signal. The interconnection is also demonstrated between a transmitting antenna and a packaged receiver 40 cm away from the transmitting antenna. Demonstration of intrachip wireless interconnects in a package has been considered the ultimate test for this technology.     

基于红外光通信电路的设计与制作

本文使用集成运放TDA2822M、红外对管作为收发器件,设计并制作出了红外载波发射电路和接收电路,实现了有限距离的红外光通信。该装置能够实现在3.0m距离范围内,接收端可接收不失真的音频信号,同时,通过监测电路可实时监测到发射端和接收端的信号情况,便于将电路调整到最佳运行状态。     

校园安防智能电话报警系统设计与实现

基于现有公共电话网络,结合射频无线通信及传感器技术,设计开发一种用于校园安防的智能报警系统。系统在探测器端上加入编码发射电路,每个探测器编码由12位组成,编码信号包括探测器的位置信息和探测器类别信息。报警终端采用无线接收方式接收编码信号,用单片机软件译码取代专用集成电路芯片硬件译码,12位编码数据位中的位置信息编码位数和探测器种类编码位数可根据实际使用场合灵活定义,突破了采用集成芯片译码只有4～6位数据位的局限性。实验结果表明:探测器无线发送距离为200 m,在8位位置信息码,4位探测器种类信息码,每位两种状态的编码方式下,每个报警终端可接入探测器的数量达256个。     

CMOS RF receiver system design: a systematic approach

A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and linearity performance of receivers are presented. Then, a few circuit examples of building blocks in receiver signal chain are analyzed to show a linear relationship between power and dynamic range of the blocks. The result is then used to derive the optimal system specification distribution among receiver signal chain building blocks yielding the minimum total receiver power consumption for a given system performance. The theory and an actual CMOS Bluetooth receiver design are compared showing very good agreement.     

基于F1596的乘积型混频器电路设计与实现

针对混频器在接收机电路中的重要性,设计实现了一种基于F1596的乘积型混频器电路。为使该电路能够输出频率稳定的信号,在电路设计中采用鉴频器取样控制VCO产生的本振信号,使该电路具有频谱纯净、失真度小、输出稳定等优点,满足了接收机混频器的使用要求。     

Demonstration of RSFQ digitizer on a multichip module

A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz     

基于FPGA的SDR FM接收机的设计

针对模拟元件制做的传统接收机的相关设备由于工作频率较高导致对元件参数要求高,电路布局布线困难等问题,提出一种利用FPGA芯片作为接收机的重要组成部分,结合简单外围硬件电路共同组成接收机的新方法。通过FPGA的差分I/O引脚完成接收机的模数转换功能,在集成设计环境Vivado中通过调用IP核的方法实现数字下变频和信号解调等功能。实验结果表明,该系统具有成本低、响应快、可靠性高的特点。