Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm²/cell, namely 3 × 2 mm²/1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-/spl mu/m transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p/sup +/ regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n/sup +/ and p/sup +/ junction depths are 0.22 /spl mu/ and of 8 /spl Omega/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Electrical Measurement of Feature Sizes in MOS Si/sup 2/-Gate VLSI Technology

The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very useful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si/sup 2/-gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 //spl mu/m.     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling

Dual mode AlGaN/GaN metal oxide semiconductor (MOS) heterostructure field-effect transistor (HFET) devices were fabricated and characterized. In HFET mode of operation the devices showed an f/sub t//spl middot/L/sub g/ product of 12GHz/spl middot//spl mu/m at Vgs=-2 V. The AlGaN devices showed formation of an accumulation layer under the gate in forward bias and a f/sub t//spl middot/L/sub g/ product of 6GHz/spl middot//spl mu/m was measured at Vgs=5 V. A novel piecewise small signal model for the gate capacitance of MOS HFET devices is presented and procedures to extract the capacitance in presence of gate leakage are outlined. The model accurately fits measured data from 45MHz to 10GHz over the entire bias range of operation of the device.     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Impact of poly-gate depletion on MOS RF linearity

The distortion behavior for thin oxide MOS transistors can be degraded due to polysilicon-gate depletion effects. The nonlinear, bias-dependent gate capacitance for thin oxide MOSFET's results in significant 2nd-order derivatives in gate capacitance, (/spl part//sup 2/C(V/sub gs/)//spl part/V/sub gs//sup 2/), which in turn results in substantial 3rd-order derivative contributions to drain current, (/spl part//sup 3/I/sub ds///spl part/V/sub gs//sup 3/). This may restrict the use of very-thin oxide MOSFET's in RF applications.     

A 150 ns, 150 mW, 64K dynamic MOS RAM

A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thickness (t/SUB ox/) transistors as active elements. Also, the RAM with a newly designed sense amplifier has successfully been fabricated using only four photo resist masking processes. The access time and power dissipation are 150 ns and 150 mW, respectively, at the cycle time of 400 ns.     

Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.     

Polysilicon oxidation self-aligned MOS (POSA MOS) — A new self-aligned double source/drain ion implantation technique for VLSI

A new MOS device named polysilicon oxidation self-aligned (POSA) MOS is proposed to enhance device performance for VLSI circuits. The device characteristics revealed significant improvement in hot-electron effects, short-channel effects and punch through voltage.     

Radiation hardness comparison of MOS capacitors using tungsten polycide and cobalt polycideas gate electrode materials

In this letter, we investigate the radiation hardness of metal-oxide-semiconductor (MOS) capacitors with tungsten polycide (WSi/sub x/) and those with cobalt polycide (CoSi/sub 2/) as gate electrode materials. CoSi/sub 2/ has been considered as a gate/contact material for MOS devices in 0.18 /spl mu/m integrated circuit fabrication due to its low resistivity and good thermal stability. However, we found that MOS capacitors with a CoSi/sub 2/ gate electrode exhibited an increase in radiation-induced interface trap density shift of more than one order of magnitude, and more than eighteen times larger in radiation-induced flatband voltage shifts compared with those with the WSi/sub x/ gate electrode, after 1 Mrad Co/sup 60/ /spl gamma/-ray irradiation under no applied bias.     

A high speed molybdenum gate MOS RAM

Describes a high speed 16K molybdenum gate (Mo-gate) dynamic MOS RAM using a single transistor cell. New circuit technologies, including a capacitive-coupled sense-refresh amplifier and a dummy sense circuit, enable the achievement of high speed performance in combination with reduced propagation delay in the molybdenum word line due to the low resistivity. The n-channel Mo-gate process was established by developing an evaporation apparatus and by an improved heat treatment to reduce surface charge density. Ultraviolet photolithography for 2 /spl mu/m patterns and HCl oxidation for 400 /spl Aring/ thick gate oxide are used. The 16K word/spl times/1 bit device is fabricated on a 3.2 mm/spl times/4.0 mm chip. Cell size is 16 /spl mu/m/spl times/16 /spl mu/m Access time is less than 65 ns at V/SUB DD/=7 V and V/SUB BB/=-2 V. Power dissipation is 210 mW at 170 ns read-modify-write (RMW) cycle.     

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

A 2.0-/spl mu/m pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.