Highly reliable SiO2/Si3N4 stackeddielectric on rapid-thermal-nitrided rugged polysilicon for high-densityDRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si ₃N₄ deposition, the quality and reliability of reoxidized Si₃N₄ dielectric (ON dielectric with an effective oxide thickness of about 35 Å) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10³ × increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress     

Trapping, conduction, and dielectric breakdown in Si3N4 films on as-deposition rugged polysilicon

Rugged polysilicon stacked capacitors recently emerged as the storage structures of choice for the manufacture of advanced DRAMs. The authors present the charge-trapping characteristics of such capacitors showing a capacitance increase of more than 50%. It is observed that electron trapping is dominant on rugged structures, whereas hole trapping is observed on smooth structures. Conduction and breakdown properties are also reported. Measurements show that rugged polysilicon capacitors provide the low leakage current, the sharp breakdown distributions, and the trapping characteristics needed for advanced DRAM applications     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

Metal gates and gate-deposition-induced defects in Ta2O5 stack capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of Ta₂O₅ stack capacitors has been investigated. The leakage currents, breakdown fields, mechanism of conductivity and dielectric constant are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode-deposition-process-induced defects acting as electrically active centers. During deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W. The sputtered W top electrode is a good candidate as a gate of storage capacitors in DRAMs, but sputtering technique is less suitable for deposition of TiN due to the introduction of radiation defects causing deterioration of leakage current. Although some reaction between Al and Ta₂O₅ occurs, the resulting electrical properties of the capacitors are still acceptable.     

Highly reliable ECR N2O-plasma polyoxide grown on heavily phosphorus-doped polysilicon films

Reliability of polyoxide grown by electron cyclotron resonance (ECR) N₂O-plasma on heavily phosphorus-doped polysilicon has been investigated for the interpoly dielectrics (IPDs) of nonvolatile memories (NVMs). ECR N₂O-plasma polyoxide grown on polysilicon with phosphorus of 1 × 10²¹ cm⁻³ exhibits a significantly high breakdown field of 10 MV/cm and low electron trapping rate of 0.5 V, which are regardless of phosphorus concentration. The improvements are attributed to the smooth polyoxide/polysilicon interface, low phosphorus concentration, and nitrogen-rich layer with strong silicon-nitrogen bonds at the polyoxide/polysilicon interface.     

High-density MIM capacitors using Al2O3 andAlTiOx dielectrics

We have investigated the electrical characteristics of Al₂ O₃ and AlTiO_x MIM capacitors from the IF (100 KHz) to RF (20 GHz) frequency range. Record high capacitance density of 0.5 and 1.0 μF/cm² are obtained for Al₂ O₃ and AlTiO_x MIM capacitors, respectively, and the fabrication process is compatible to existing VLSI backend integration. However, the AlTiO_x MIM capacitor has very large capacitance reduction at increasing frequencies. In contrast, good device integrity has been obtained for the Al₂O₃ MIM capacitor as evidenced from the small frequency dependence, low leakage current, good reliability, small temperature coefficient, and low loss tangent     

Thin RF sputtered and thermal Ta2O5 on Si for high density DRAM application

Tantalum pentoxide thin films on Si prepared by two conventional for modern microelectronics methods (RF sputtering of Ta in Ar + O₂ mixture and thermal oxidation of tantalum layer on Si) have been investigated with respect to their dielectric, structural and electric properties. It has been found that the formation of ultra thin SiO₂ film at the interface with Si, during fabrication implementing the methods used, is unavoidable as both, X-ray photoelectron spectroscopy and electrical measurements, have indicated. The initial films (as-deposited and as-grown) are not perfect and contain suboxides of tantalum and silicon which act as electrical active centers in the form of oxide charges and interface states. Conditions which guarantee obtaining high quality tantalum oxide with dielectric constant of 32–37 and leakage current density less than 10⁻⁷ A/cm² at 1.5 V applied voltage (Ta₂O₅ thickness equivalent to about 3.5 nm of SiO₂) have been established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAM application.     

Influence of the metal electrode on the characteristics of thermal Ta2O5 capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta₂O₅ capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta₂O₅ thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta₂O₅ during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta₂O₅, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta₂O₅ capacitors with a good quality: the current density <7 × 10⁻¹⁰ A/cm² at 1 V (0.7 MV/cm, 15 nm thick Ta₂O₅). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta₂O₅ as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta₂O₅, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics.     

Characteristics of MIS capacitors based on multilayer TiO2–Ta2O5 structures

We report electrical characteristics of multilayer TiO₂–T₂O₅ based MIS structures obtained by simple electron beam evaporation and annealed in an O₂ environment. We describe parameter dependence on annealing conditions and demonstrate an equivalent SiO₂ thickness of 3 nm with a leakage current density of 10⁻⁷ A/cm² at an electric field of 10⁶ V/cm.     

Dielectric reliability of stacked Al2O3–HfO2 MIS capacitors with cylinder type for improving DRAM data retention characteristics

Dielectric reliability in Al₂O₃(2–3.1nm)–HfO₂(3nm) stack capacitor with Metal–Insulator–Si(MIS) structure is investigated in this paper. We propose an optimized capacitor process through the Time–Dependent Dielectric Breakdown (TDDB) data under various process conditions. Furthermore, due to asymmetric current at both negative and positive voltage stress polarities, we show different lifetime extrapolation by a fluence–driven model. As a result, the maximum allowed operating voltage is projected to be 1.7V (failure rate 10ppm during 10year @ 85°C) for Data “0” retention lifetime.     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Dependence of electrical properties on interfacial layer of Ta2O5 films

The change in the thickness and chemical states of the interfacial layer and the related electrical properties in Ta₂O₅ films with different annealing temperatures were investigated. The high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the 700 °C-annealed Ta₂O₅ film remained to be amorphous and had the thinnest interfacial layer which was caused by Ta-silicate decomposition to Ta₂O₅ and SiO₂. In addition, the electrical properties were improved after annealing treatments. Our results suggest that an annealing treatment at 700 °C results in the highest capacitance and the lowest leakage current in Ta₂O₅ films due to the thinnest interfacial layer and non-crystallization.     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

H2/O2 plasma on polysilicon thin-filmtransistor

It is reported for that H₂ plasma followed by O₂ plasma is more effective for passivating grain boundary states in polysilicon thin film. Polysilicon thin-film transistors (TFTs) made after H₂/O₂ plasma treatment can exhibit a turn-on threshold voltage of -0.1 V, a subthreshold swing of 0.154 V/decade, an ON/OFF current ratio I_on/I_off over 1×10⁸, and an electron mobility of 40.2 cm² /V-s     

用于GaAs射频集成电路的不同厚度氧化铝MIM 电容的研究

本文研究了不同厚度的氧化铝对MIM电容直流和射频特性的影响。在1MHz下,对于20nm氧化铝MIM电容,其拥有3850 pF/mm₂的高电容密度和可接受的681 ppm/V₂的VCC-α电压系数。1MHz时突出的74 ppm/V₂VCC-α电压系数,8.2GHz谐振频率以及2GHz时41的Q值可以从100nm氧化铝MIM电容获得。采用GaAs工艺以及原子层淀积制造的高性能ALD氧化铝MIM电容很有可能成为GaAs射频集成电路很有前景的候选器件。     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Structural properties of V2O5 thin films prepared by vacuum evaporation

Vanadium pentoxide (V₂O₅) films were deposited on glass substrates by vacuum evaporation technique at various deposition temperatures (T_s) viz., 300, 473, 573, 623 and 673 K. The structural and microstructural properties of the films are analyzed using XRD and Raman scattering measurements. X-ray characterization revealed the films deposited at T_s473 K are amorphous and the film deposited at T_s573 K are polycrystalline with orthorhombic symmetry. The corrected lattice constant values are determined from Nelson-Riely plots. The lattice constants “a” and “c” are found to decrease with increase in the deposition temperature, which may be attributed to the increase in non-stoichiometry. Change in the preferred orientation is observed for films deposited at substrate temperatures 623 K which is likely to be governed by the recrystallization process. Various structural parameters such as lattice constants, grain size, and microstrain and dislocation density are determined and the influence of deposition temperature on the structural parameters are discussed.     

Low Rayleigh scatteringP2O5-F-SiO2 glasses

The Rayleigh scattering and infrared absorption losses of P₂ O₅-F-doped silica glass, which is a candidate material for ultra-low-loss optical fiber, were investigated experimentally. The Rayleigh scattering loss of 8.5 wt.% P₂O₅ and 0.3 wt.% F-doped SiO₂ glass is found to be 0.8 times that of pure silica glass. It is also found that the infrared absorption property of P₂O₅-F-SiO₂ glass is almost the same as that of pure silica glass. The minimum loss for the proposed composition is estimated to be 0.11 dB/km at 1.55 μm wavelength, and 0.21 dB/km at 1.3 μm wavelength