Effects of post-deposition annealing on the electrical propertiesand reliability of ultrathin chemical vapor deposited Ta2O5 films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta₂O₅ (~10 nm) on NH₃-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800°C rapid thermal O₂ annealing (RTO) for 20 sec followed by rapid thermal N₂ annealing (RTA) for 40 sec, b) 800°C RTO for 60 sec and c) 900°C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta₂O₅/poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics     

Highly reliable SiO2/Si3N4 stackeddielectric on rapid-thermal-nitrided rugged polysilicon for high-densityDRAM's

Experimental results are presented demonstrating that by using rapid thermal nitridation (RTN) of rugged poly-Si surface prior to Si ₃N₄ deposition, the quality and reliability of reoxidized Si₃N₄ dielectric (ON dielectric with an effective oxide thickness of about 35 Å) can be significantly improved over ON films on rugged poly-Si without RTN treatment. These improvements include significantly reduced defect-related dielectric breakdown, 10³ × increase in TDDB lifetime, lower leakage current, and suppressed electron-hole trapping and capacitance loss during stress     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Leakage current reduction in chemical-vapor-depositedTa2O5 films by rapid thermal annealing in N2O

This study aims to improve the electrical characteristics and reliability of low-pressure chemical vapor deposited (LPCVD) Ta₂ O₅, films by developing a new post-deposition single-step annealing technique. Experimental results indicate that excited oxygen atoms generated by N₂O decomposition can effectively repair the oxygen vacancies in the as-deposited CVD Ta₂ O₅ film, thereby resulting in a remarkable reduction of the film's leakage current. Two other post-deposition annealing conditions are compared: rapid thermal O₂ annealing and furnace dry-O₂ annealing. The comparison reveals that RTN₂O annealing has the lowest leakage current, superior thermal stability of electrical characteristics and the best time-dependent dielectric breakdown (TDDB) reliability     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

Reduction of leakage current in chemical-vapor-deposited Ta2O5 thin films by furnace N2O annealing

In this brief, we present a post-deposition annealing technique that employs furnace annealing in N₂O (FN₂O) to reduce the leakage current of chemical-vapor-deposited tantalum penta-oxide (CVD Ta₂O₅) thin films. Compared with furnace annealing in O₂ (FO) and rapid thermal annealing in N ₂O (N₂O), FN₂O annealing proved to have the lowest leakage current and the most reliable time-dependent dielectric breakdown (TDDB)     

Fabrication and characterization of Si-MOSFET's with PECVDamorphous Ta2O5 gate insulator

Silicon MOS transistors having amorphous Ta₂O₅ insulator gates have been fabricated. The Ta₂O₅ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF₅. Electrical characteristics of p-channel Al gate transistors are presented     

Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Superior low-pressure-oxidized Si3N4 films onrapid-thermal-nitrided poly-Si for high-density DRAM's

High-performance stacked storage capacitors with small effective-oxide-thickness (t_ox,eff) as thin as 37 Å has been achieved using low-pressure-oxidized nitride films deposited on NH ₃-nitrided poly-Si electrodes. The capacitors exhibit excellent leakage property and time-dependent dielectric-breakdown (TDDB) characteristics. Furthermore, this technique is promising for the 64- and 256-Mb dynamic-random-access-memory (DRAM) applications because the process temperatures never exceed 850°C     

Dual Process Dielectric Formation for Decoupling Capacitors on Flexible Substrates

Large area, high density integrated capacitors within printed wiring boards can provide a substantial decoupling capacitance with very low parasitic inductance. Tantalum pentoxide (Ta₂O₅) is an excellent dielectric for this application due to the relatively high dielectric constant (~ 22-24), however the difficulty of fabricating large, defect-free capacitors has thus far prevented the realization of practical applications. This work demonstrates high performance capacitors with Ta₂O₅ dielectric developed with a two step oxidation scheme consisting of reactive sputtering followed by anodization. Thin films of Ta₂O₅ were deposited by reactive sputtering on silicon and also on Upilex^reg covered glass wafers using dc magnetron sputtering with a gas flow ratio of 10/90 O₂/Ar. In the two-step oxidation scheme, anodization is performed after reactively sputtering tantalum oxide films to obtain a densifled oxide structure. The electrical and physical properties of these two step sputtered/ anodized tantalum oxide films are shown to be superior to those of tantalum oxide films prepared by either anodization or sputtering alone. This work has shown that Ta₂O₅ is a potential dielectric for integrated capacitors that could be used in advanced packaging applications.     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Low-loss polyimide-Ta2O5-SiO2hybrid ARROW waveguides

A low-loss polyimide-Ta₂O₅-SiO₂ hybrid antiresonant reflecting optical waveguide (ARROW) is presented. The ARROW device was fabricated using both the organic and dielectric thin-film technologies. It consists of the fluorinated polyimide, tantalum pentoxide (Ta₂O₅), and silicon dioxide (SiO₂) hybrid layers deposited on a Si substrate. For transverse electric polarized light, the propagation loss of the waveguide as low as 0.4 dB/cm was obtained at 1.31 μm. The propagation loss for transverse magnetic polarized light is 1.5 dB/cm. An ARROW waveguide fabricated using the polyimide-Ta₂O₅ -polyimide material system is also presented for comparison     

Studies of yttrium oxide films prepared by RF magnetron sputtering

Films of yttrium oxide (Y₂O₃) were deposited on Si substrates from a Y₂O₃ target by RF magnetron sputtering. MIS capacitors in the form of Al and Y₂O₃ (400 Å)-Si were then fabricated. The leakage current density was about 10^-6 A/cm² at 1.3×10⁶ V/cm, and the breakdown field of the films was about 2.75×10⁶ V/cm. The dielectric constant of the sputtered Y₂O₃ was found to be about 12-12.7     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

Charge trapping and degradation in high-permittivityTiO2 dielectric films

Suitable replacement materials for ultrathin SiO₂ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO₂, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown (TDDB), and capacitance-voltage (C-V) measurements were done on 190 Å layers of TiO₂ which were deposited through the metal-organic chemical vapor deposition (MOCVD) of titanium tetrakis-isopropoxide. Measurements of the high- and low-frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage current upon electrical stress may be due to the creation of uncharged, near interface states in the TiO₂ film near the SiO₂ interfacial layer that give rise to increased tunneling leakage