共查询到19条相似文献,搜索用时 171 毫秒
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研究了用Ag-Sn作为键合中间层的圆片健合。相对于成熟的Au-Sn键合系统(典型键合温度是280℃),该系统可以提供更低成本、更高键合后分离(De-Bonding)温度的圆片级键合方案。使用直径为100mm硅片,盖板硅片上溅射多层金属Ti/Ni/Sn/Au,利用Lift-off工艺来形成图形。基板硅片上溅射Ti/Ni/Au/Ag。硅片制备好后,将盖板和基板叠放在一起送入键合机进行键合。键合过程在N2气氛中进行,键合过程中不需要使用助焊剂。研究了不同键合参数,如键合压力、温度等对键合结果的影响。剪切强度测试表明样品的剪切强度平均在55.17MPa。TMA测试表明键合后分离温度可以控制在500℃左右。He泄漏测试证明封接的气密性极好。 相似文献
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硅片直接键合机理及快速热键合工艺 总被引:4,自引:0,他引:4
本文的理论与实验结果说明,硅片表面吸附的OH团是室温下硅片相互吸引的主要根源。采用SIMS和红外透射谱定量测量了OH吸附量。开发了表面活化技术。发现键合强度随温度而增大是键合面积增加所致。SiO_2/SiO_2键合之界面中各种物质的扩散及氧化层粘滞流动可以消除界面微观间隙。经表面活化的两硅片经室温贴合,150℃预键合,800℃,2小时退火后经1200℃,2分钟快速热键合可实现完善的键合且原有杂质分布改变很小,为减薄工艺提供了一个技术基础。 相似文献
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在采用Si-玻璃阳极键合技术制备微惯性传感器的过程中,实验发现键合圆片中心区域键合失效。通过对键合机理和工艺过程进行分析,认为湿法腐蚀工艺引入钾离子(K+)污染是造成键合失效的主要原因,也可以对键合失效现象给出合理的解释。改变工艺参数进行了键合对比实验,结果表明,未受K+污染的键合圆片没有发生键合失效现象。提出了解决键合失效问题的两种方案,并首次提出在Si片表面生长氧化层提高失效区键合强度的方法;从理论上分析了增加SiO2介质层的可行性。强度测试结果表明,在SiO2厚度为150nm时,键合剪切强度达到14MPa,验证了方案的可靠性。利用上述方法制备出微加速度传感器敏感结构。 相似文献
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简要介绍了晶圆键合技术在发光二极管(LED)应用中的研究背景,分别论述了常用的黏合剂键合技术、金属键合技术和直接键合技术在高亮度垂直LED制备中的研究现状,包括它们的材料组成和作用、工艺步骤和参数以及优缺点.其中,黏合剂键合是一种低温键合技术,且易于应用、成本低、引入应力小,但可靠性较差;金属键合技术能提供高热导、高电导的稳定键合界面,与后续工艺兼容性好,但键合温度高,引入应力大,易造成晶圆损伤;表面活化直接键合技术能实现室温键合,降低由于不同材料间热失配带来的负面影响,但键合良率有待提高. 相似文献
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通过三步直接键合方法实现了 Si/ Si键合。采用 XPS、FTIR、I-V、拉伸强度等手段对 Si/ Si键合结构的界面特性作了深入广泛的研究。研究结果表明 ,高温退火后 ,在键合界面没有 Si-H和 Si-OH网络存在 ,键合界面主要由单质 Si和不定形氧化硅 Si Ox 组成。同时 ,研究还表明 ,I-V特性和键合强度强烈地依赖于退火温度。 相似文献
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Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor
devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants
betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must
be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low
temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated
surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the
reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra
high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer
requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region
by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto
a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy
is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic
in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high
temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to
be within a temperature window that is specific for each material. The experimentally determined temperature windows for some
semiconductors and single crystalline oxides will be given. 相似文献
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A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding
duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications.
In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed
and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature,
duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C
bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is
necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding
condition for 3-D integration can be determined. 相似文献
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