共查询到19条相似文献,搜索用时 171 毫秒
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随着半导体技术的进步,对A/D、D/A转换器的性能提出了更高的要求,用于制作A/D、D/A转换器的工艺技术也在不断改进.文章介绍了目前用于制作A/D、D/A转换器的主流工艺技术;结合相关产品,对比分析了各种工艺的优缺点,并对A/D、D/A转换器工艺技术的发展趋势进行了展望. 相似文献
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高速A/D转换器的研究进展及发展趋势 总被引:1,自引:0,他引:1
介绍了高速高精度A/D转换器技术的发展情况、A/D转换器的关键指标和关键技术考虑;阐述了高速高精度A/D转换器的结构和工艺特点;讨论了高速高精度A/D转换器的发展趋势. 相似文献
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本文从D/A与A/D转换器的基本概念和制造技术着手概述,特别对D/A和A/D转换器的应用之主要选择因素,进行了着重说明。随后,提出了D/A和A/D转换器优化品种的原则意见。 相似文献
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介绍了一种16位D/A转换器抗辐射加固设计和工艺技术。主要从系统结构加固设计、关键单元加固设计和工艺加固技术等方面进行了阐述;重点对BiCMOS加固工艺的器件结构设计原理进行了详细阐述,给出了器件仿真数据和实验结果;最后,对辐照试验进行了分析。采用该加固工艺研制的16位D/A转换器实现了转换速率大于30 MSPS,建立时间小于50 ns,线性误差和微分误差均小于±8 LSB等性能指标;其抗中子辐射水平为5×1013n/cm2,抗γ总剂量辐射水平达5.0×103Gy(Si)。 相似文献
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高速A/D转换器测试采样技术研究 总被引:3,自引:0,他引:3
高速A/D转换器是电子器件中比较特殊而又关键的器件。关于高速A/D转换器的动态参数测试方法比较多,文章主要讨论相干采样与加窗采样在高速A/D转换器参数测试中的应用,两种方法各自的优缺点,以及应用中应该注意的问题。 相似文献
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A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology 相似文献
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介绍了数据转换器的市场规模及其发展趋势,高速A/D转换器的主要研发公司及其代表产品水平,主流产品的电路结构和工艺技术以及技术发展趋势。 相似文献
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首先分别介绍了当前六大模数转换技术的工作原理、电路结构、性能特点及应用领域,通过从转换速率、转换精度、分辨率、功耗、价格、面积等指标进行分析,将物理结构的设计与实际性能结合比较,总结出各自适合的应用领域.然后,根据对现有模数转换技术特点的分析及实际应用中对模数转换器性能的要求,对当前A/D转换技术向着高性能、低功耗、结构简单方向发展的趋势进行了预测. 相似文献
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Switched-current oversampling A/D converters are the ideal choice for mixed analog/digital design due to their complete compatibility with digital CMOS process and high tolerance to process variation. This paper presents a tutorial discussion on all the aspects of switched-current oversampling A/D converters, including structures, circuits, and practical issues. Three different modulator structures and six different types of switched-current circuits were used with an emphasis on low-voltage operation. Eight 3.3-V oversampling A/D converters were implemented and measured, and another one 1.2-V oversampling A/D converter was also implemented but yet to be measured. 相似文献
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A/D转换器(ADC)的校准技术是提高高性能ADC转换精度的必要手段,它分为模拟校准技术和数字校准技术。数字校准技术较之模拟校准技术更为有效和更具灵活性。数字校准技术是在数字域进行错误代码计算,减轻了对模拟电路的精度要求。在主流制造工艺小尺寸化的趋势之下,许多创新的校准技术得到发展,并广泛应用于包括射频直接采样ADC在内的高速高精度ADC中。本文在分析最新的高速高精度ADC中采用的主要校准技术的基础上,重点研究了几种高采样率高精度ADC所采用的校准技术,侧重分析了数字校准技术。 相似文献
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Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW. 相似文献
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Lee H.-S. Brooks L. Sodini C. G. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2010,98(2):315-332
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Emerging telecom systems such as ADSL and VDSL demand state-of-the-art high speed and high resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DBCs). Moreover, cost and power consumption issues require the use of specific A/D and D/A architectures to achieve the wanted resolution at the required speed at minimum power. In the first part of this article we present an overview of the various ADC and DAC architectures used in Alcatel Telecom systems over the past 15 years, with an emphasis placed on the evolution of ADCs and DACs for today's asymmetrical-digital-subscriber-loop (ADSL) applications. We then discuss design considerations for high-speed and high resolution ADCs for future very-high-data-rate digital subscriber-line (VDSL) technology 相似文献
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《Solid-State Circuits, IEEE Journal of》1979,14(6):912-920
A new multiple-differential-voltage input, MOS, sampled-data, `charge-balance' comparator which can `weight' or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 Rs and 32 switches as compared to the 256 Rs and 512 switches of a standard 2/SUP N/R ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 Rs and 64 switches instead of 8192 Rs and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset. 相似文献