Schottky I/SUP 2/L

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.     

Schottky collector I/SUP 2/L

A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.     

Schottky I/SUP 2/L (substrate fed logic)-an optimum form of I/SUP 2/L

A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.     

Frequency dividers by Schottky coupled I/SUP 2/L gates

A frequency dividing cell composed of four I/SUP 2/L gates and two Schottky diodes is proposed and analyzed. The cells are connected by one I/O line. n-p-n transistors need only two collectors. Simulation of the circuit with I/SUP 2/L gates of 3.2 ns/gate predicts the operating frequency up to 80 MHz. The operating frequency of 33 MHz was observed using a circuit built by discrete I/SUP 2/L gates with minimum propagation delay of 7.5 ns/gate and Schottky diodes.     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

Schottky-base I/SUP 2/L: a high-performance LSI technology

A new I/SUP 2/L technology is described which offers significant advantages in packing density, device performance, and reduced LSI circuit complexity as compared to the conventional I/SUP 2/L. The basic logic gate in this design is a multiinput, multioutput NAND gate which consists of a p-n-p switch and an n-p-n injector. Schottky diodes are formed on the p-n-p base which is merged with the n-p-n (injector) collector. This I/SUP 2/L technology also offers convenient interfacing with other standard IC parts. Experimental data on a test chip indicate a p-n-p current gain of ~50, TTL-type n-p-n current gain of ~80, a delay-power product of 0.5 pJ, and a minimum delay of 10 ns for devices using 7.5 /spl mu/m minimum linewidths.     

High-speed split-emitter I/SUP 2/L/MTL memory cell

Describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I/SUP 2/L/MTL memory cell cited in a 16-kbit static MTL RAM (see IEEE ISSCC Dig. Tech. Papers, p.222-4, 1980). As a result, a compact memory cell with extremely low DC standby power in the nanowatt range and with read/write times below 5 ns is achieved. This has been verified by experimental investigations on small test arrays. They have been fabricated with an advanced process featuring a p-polysilicon-base self-alignment scheme and a double-diffused p-n-p structure. In addition, computer circuit simulations have been performed that show the read delay sensitivities in large arrays. Based on these results, an access time of less than 25 ns is projected for a 16-kbit MTL RAM.     

Linear compatible I/SUP 2/L technology with high voltage transistors

A technology is proposed in which it is possible to realize both I/SUP 2/L circuits and linear transistors with V/SUB CBO/ of 60 V. The essential step in such a technology is an additional n/SUP +/-flat diffusion. The technological parameters are derived. From measurements on wafers processed in the outlined technology. The author established functioning I/SUP 2/L elements and high voltage transistors.     

Considerations for high-speed and analog-circuit-compatible I/SUP 2/L and the analysis of Poly I/SUP 2/L

Expressions are derived for minimum propagation-delay time and DC operational conditions in the I/SUP 2/L circuit configuration, and are applied to several kinds of I/SUP 2/L limitations. 1) Ultimately achievable (roughly 0.34 ns, fan-out of 2) and reasonably expected minimum propagation-delay values (0.75-1.0 ns considering simple n-p-n limitations) are estimated. 2) Speed improvements of the standard I/SUP 2/L structure via doping level adjustment is shown to be minimal (it is primarily useful for ensurance of DC operation). 3) Requiring analog compatibility further constrains performance; a figure of merit of about 1 to 2 V/ns is derived and experimentally confirmed for the product of analog device BV/SUB CBO/ and I/SUP 2/L speed for standard epitaxial I/SUP 2/L processing. Radical techniques using dual buried layers, dual epitaxial layers, or Poly I/SUP 2/L offer considerably enhanced performance by attacking the parameter with primary leverage on these tradeoffs: base-to-buried layer spacing W/SUB epi/. Analysis of Poly I/SUP 2/L reveals specific advantages.     

Processing technology and AC/DC characteristics of linear compatible I/SUP 2/L

The processing, a.c. and d.c. characteristics of I/SUP 2/L structures integrated with common analog circuit elements are studied. Since the required breakdown voltage of the analog circuitry normally dictates the resistivity and thickness of the silicon epitaxial layer, the authors studied the parametric performance of the I/SUP 2/L structure for common linear circuit voltages. Design criteria, processing, and device performance are presented for I/SUP 2/L structures built on several different types of material. The I/SUP 2/L performance achieved in the linear compatible technology easily allowed a fan-out of four and gate propagation delay less than 50 ns with standard device breakdowns of 20 V; but fan-out is limited to three and gate delay to 100 ns for the process which attained 30-V breakdowns.     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

5/spl times/9 integrated optical star coupler in silicon-on-insulator technology

We describe fabrication of the first optical star coupler in silicon-on-insulator (SOI) technology. The 5/spl times/9 coupler consists of two silicon rib waveguide arrays with a radiative slab waveguide region. The star geometry was analyzed and designed using the beam propagation method. The coupler exhibits low loss (average excess insertion loss /spl alpha//spl sim/1.3 dB) and good coupling uniformity (standard deviation /spl sigma//spl sim/1.4 dB) at /spl lambda/=1.55 /spl mu/m. It represents a key component for realization of photonic circuits in a silicon integrated circuit technology.     

Schottky I/SUP 2/L (substrate fed logic)-an analysis of the implications of the vertical injector structure and Schottky collection

The DC behavior of a Schottky I/SUP 2/L gate is analysed by using the Ebers-Moll equations, modified to include Schottky diodes. The usual definition of I/SUP 2/L common emitter current gain is replaced by a new definition which is more suitable for the vertical injector structure of Schottky I/SUP 2/L. The analysis is general and can be applied to any multijunction structure containing Schottky diodes or having a distributed current source. This framework is used to examine the effect on the fan-out of minority carrier collection at the Schottky contacts. Equations are presented which relate both the recombination at the Schottky contacts and the vertical reinjection through the inverse p-n-p transistor to the device structure.     

Beta measurement and beta requirement in I/SUP 2/L gates

A new approach to beta measurement in the inversely operated I/SUP 2/L transistor is described, one that avoids arbitrary definitions and terminal-condition specifications. The authors deactivate the lateral p-n-p by symmetrical biasing so that direct measurement of n-p-n base current becomes possible. Further measurements demonstrate the validity of this approach, and also determine the beta necessary for a desired saturation voltage.     

A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology

Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage capacitor is provided by the adjacent word line. This layout achieves the same density as the conventional double-polysilicon cell, and comparable performance is obtained using a low-resistance polycide word line. Hi-C implants in the storage region provide increased capacitance, better isolation, and reduced transient noise. Design and operation considerations for the cell and arrays are described and measured results are compared to the design values. A cell area of 34 /spl mu/m/SUP 2/ is achieved using a scaled-down n-channel FET technology with a 22.5 nm gate oxide and 1 /spl mu/m minimum mask feature size.     

A 60 ns 256K/spl times/1 bit DRAM using LD/SUP 3/ technology and double-level metal interconnection

A high-speed 256K/spl times/1-bit DRAM, using new circuit design techniques and a scaled n-channel process, has been developed. A row access time of 60 ns has been achieved through the use of short-channel devices and two levels of low-resistance interconnect. A staggered matrix precharge was implemented to reduce peak supply current and dI/dt during row precharge. Supply current transients are particularly important at the 256K density level due to the fast cycle rates (approaching 10 MHz) and the large matrix capacitance to be precharged.     

Threshold I/SUP 2/L and its applications to binary symmetric functions and multivalued logic

I/SUP 2/L threshold gate using current mirrors providing weighting of inputs, summation, and comparison with a threshold is described and its practical realization is discussed. Application to binary symmetric functions shows significant area savings over standard I/SUP 2/L implementation. A complete multivalued logic family, using a four-level I/SUP 2/L threshold logic technique is introduced.     

A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technology

For a comparison of different single-transistor cell designs and sense/refresh amplifier designs figures of merit are derived from the quasi-static behavior of the memory circuit during sensing. The principles of the different cell designs are discussed. A cell with the most favorable design has been realized with a standard n silicon-gate process sequence and contact photolithography. It uses aluminum word lines of 5 /spl mu/m width and separation, a contact hole with a size of 4 /spl mu/m to 6 /spl mu/m, and diffused bit lines with a width of 4 /spl mu/m. For the 1-mil/SUP 2/ memory cell a sense/refresh amplifier based on the gated flip-flop principle has been realized. The sensitivity of this amplifier, which is determined by the integrated circuit element tolerances is estimated and measured.     

A new circuit configuration for a static memory cell with an area of 880 /spl mu/m/SUP 2/

A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced.     

The TDA1077-an I/SUP 2/L circuit for two-tone telephone dialing

The circuit-design aspects of an integrated circuit to perform two-tone telephone dialing are described. The circuit is believed to be unique in that it combines both the crystal-controlled frequency synthesizer and the output amplifier on the same chip. Moreover, no external power supplies are required; the circuit is powered by the telephone-line current. Designed to require a minimum number of external components, the LSI chip provides an economical and accurate two-tone dialing unit. A typical application circuit for existing telephone apparatus is shown and aspects of future development are discussed.