A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits

A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.     

ISL, a fast and dense low-power logic, made in a standard Schottky process

Integrated Schottky logic (ISL) is a new 200 mV voltage-swing LSI logic that can be made in standard Schottky processes with a double-layer metallization. It fills the gap between low-power Schottky TTL and I/SUP 2/L for those circuits where low-power Schottky TTL consumes too much power and takes up too much chip area, and when I/SUP 2/L does not attain the required speed. An ISL gate consists of a current source and a set of Schottky output diodes (wired AND gate). Minimum propagation delay times of 2.7 ns at 200 /spl mu/A/gate are obtained, with a speed-power product of 1.2 pJ. The packing density of ISL is 120 to 180 gates/mm/SUP 2/. The logic can be combined with ECL, I/SUP 2/L, and TTL on the same chip, and can also be made in analog processes.     

Schottky I/SUP 2/L

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.     

Schottky collector I/SUP 2/L

A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.     

Schottky-base I/SUP 2/L: a high-performance LSI technology

A new I/SUP 2/L technology is described which offers significant advantages in packing density, device performance, and reduced LSI circuit complexity as compared to the conventional I/SUP 2/L. The basic logic gate in this design is a multiinput, multioutput NAND gate which consists of a p-n-p switch and an n-p-n injector. Schottky diodes are formed on the p-n-p base which is merged with the n-p-n (injector) collector. This I/SUP 2/L technology also offers convenient interfacing with other standard IC parts. Experimental data on a test chip indicate a p-n-p current gain of ~50, TTL-type n-p-n current gain of ~80, a delay-power product of 0.5 pJ, and a minimum delay of 10 ns for devices using 7.5 /spl mu/m minimum linewidths.     

Modeling of the diode input I/SUP 2/L structure

A high-speed single-collector multiinput Schottky diode I/SUP 2/L structure is presented. The structure features negligible p-n-p and a relatively low extrinsic base minority carrier storage, and lends to the near elimination of saturation. A theoretical model predicts that the structure produces circuit delays of better than 3 ns at 50 /spl mu/A.     

(MI)/SUP 2/L: multiinput-multioutput integrated injection logic

The (MI)/SUP 2/L structure will be discussed, which is a combination of CHL/CHIL and I/SUP 2/L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I/SUP 2/L schemes. The gate consists of a lateral n-p-n transistor with intermediate collectors and a Schottky inverter. The device fabrication is fully compatible with standard bipolar processes for analog circuits. The approach is applied to a standard bipolar process of 6 /spl mu/m epi thickness and 35 V breakdown voltage. The results obtained are a minimum power-delay product of 0.07 pJ and a minimum delay of 17 ns at 0.38 pJ. The improved device parameters, packing density, and design flexibility are discussed with the experimental results of test circuits, including a D-type frequency divider and MS flip-flop.     

A 90 ns 256K /spl times/ 1 bit DRAM with double-level Al technology

A high-performance 256K /spl times/ 1bit DRAM with double-level Al technology is described. It has a small die size of 8.5 /spl times/ 4.0 mm/SUP 2/, an access time of 90 ns, and a soft error rate of less than 1000 FITs. The first and second Al layers are used as bit lines and word lines, respectively. Double-level Al technology is also applied to periphery circuit regions and contributes to a 15 percent reduction of die size in conjunction with a simplified sense-restore circuit. A compact memory cell (10.9 /spl times/ 6.1/spl mu/m /SUP 2/) with a storage capacitance of over 50 fF is obtained through the use of wafer stepping and dry etch techniques.     

Schottky I/SUP 2/L (substrate fed logic)-an analysis of the implications of the vertical injector structure and Schottky collection

The DC behavior of a Schottky I/SUP 2/L gate is analysed by using the Ebers-Moll equations, modified to include Schottky diodes. The usual definition of I/SUP 2/L common emitter current gain is replaced by a new definition which is more suitable for the vertical injector structure of Schottky I/SUP 2/L. The analysis is general and can be applied to any multijunction structure containing Schottky diodes or having a distributed current source. This framework is used to examine the effect on the fan-out of minority carrier collection at the Schottky contacts. Equations are presented which relate both the recombination at the Schottky contacts and the vertical reinjection through the inverse p-n-p transistor to the device structure.     

Frequency dividers by Schottky coupled I/SUP 2/L gates

A frequency dividing cell composed of four I/SUP 2/L gates and two Schottky diodes is proposed and analyzed. The cells are connected by one I/O line. n-p-n transistors need only two collectors. Simulation of the circuit with I/SUP 2/L gates of 3.2 ns/gate predicts the operating frequency up to 80 MHz. The operating frequency of 33 MHz was observed using a circuit built by discrete I/SUP 2/L gates with minimum propagation delay of 7.5 ns/gate and Schottky diodes.     

A new high-voltage analog-compatible I/SUP 2/L process

A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.     

Schottky I/SUP 2/L (substrate fed logic)-an optimum form of I/SUP 2/L

A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.     

High density COS/MOS 1024-bit static random access memory

A static 1024/spl times/1 self-aligned silicon-gate COS/MOS random access memory (RAM) has been developed using `self-registry' techniques to achieve high packing density. The techniques developed permitted a 7500 transistor COS/MOS memory circuit to be fabricated in a 0.134/spl times/0.168 in/SUP 2/ chip, with a 13.4 mil/SUP 2/ six transistor cell. Such packing density is approximately five times that of conventional metal-gate COS/MOS circuits. The merits of fabricating such devices using an advanced process technique based on all ion-implanted diffusions to enhance yields have also been studied.     

Circuit techniques for a 25 ns 16K/spl times/1 SRAM using address-transition detection

The authors describe special circuit techniques that have been used to produce a 25-ns HMOS 16K/spl times/1 SRAM. In particular, a new dynamic row-decoder driver, hold-valid-data output driver, and column-decoder driver have been developed. A new memory clear function, called the bulk-write feature, that writes all data locations to the same data as the data-in pin in one long (/spl sime/700 ns) write cycle was also developed. This 16K/spl times/1 SRAM has a die area of 25.3K mil/SUP 2/ (16.3 mm/SUP 2/), and was fabricated using a 2-/spl mu/m double-polysilicon NMOS technology.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

Poly I/SUP 2/L-a high-speed linear-compatible structure

Poly I/SUP 2/L a new bipolar process technology, is presented featuring 5 ns minimum propagation delay, 24 MHz flip-flop operation (using 10 /spl mu/ minimum feature size), and 15-30 V isolated and unconstrained linear circuit transistors on 5 /spl Omega/.cm epitaxy. Standard linear integrated circuit process complexity is increased by only one mask without extra diffusions.     

A 30 ns 16K/spl times/1 fully static RAM

A fully static 16K/spl times/1 random access memory (SRAM) with significantly improved speed is discussed. Design innovations using conservative 2.5 /spl mu/m transistors and state-of-the-art double level poly (DLP) scaled NMOS technology were utilized to accomplish 30 ns address and chip select access times with an active power of 550 mW and standby power of 75 mW. A cost effective DLP process was developed using `shared' contacts in the cell. These `shared' contacts utilize second level poly to provide connection between the first poly level and moat, reduced the number of contacts per cell to four. The DPL cell size is 1.6 mil/SUP 2/ (1000 /spl mu/m/SUP 2/) which yields a bar size of 158/spl times/264 mil/SUP 2/ (4.0/spl times/6.7 mm/SUP 2/). In this fully static design a novel architecture was used to power down half of the X-decoders in the active mode using the AO address buffer signals. This technique allowed the use of power saved in the X-decoder to be distributed throughout the circuit to improve overall access times. One of the other major speed improvements came from utilizing column sense amps. The use of the column sense amp improves the overall speed by more than 20 percent. A write cycle of 30 ns has been achieved with a typical write pulse width of 10 ns.     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.