An integrated circuit for GSM mobile communications

An integrated circuit for the Pan European GSM mobile communications system is described which performs GMSK digital modulation and front-end functions for both base and mobile stations. The circuit includes, as main functional blocks, a 10-bit D/A converter, a 13-MHz switched-capacitor interpolating filter, and a power buffer. A fully differential approach was used. The circuit has been fabricated using a 2-m CMOS process. The chip size is 6.7×5.3 mm². The overall circuit performance fully meets GSM specifications.     

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.     

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150$~$nm, 1.5 $~$V CMOS and 240$~$nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.      

A Low Power 8 x 8 Direct 2-D DCT Chip Design

This paper presents the design and implementation of a low power 8 × 8 2-D DCT chip based on a computation-effective algorithm. Computational complexity can be reduced by simplifying the direct 2-D algorithm. Thus, the low power consumption is achieved due to complexity reduction. Besides, the parallel distributed-arithmetic (DA) technique is used to realize constant multiplication due to the low-power consideration. Additionally, the 2 V-power supply is practiced in circuit implementation for now and future battery operated applications. By using the TSMC 0.6 m single-poly double-metal technology, 133 mW power consumption at 100 MHz and the 133 MHz maximum operation speed are achieved by critical path simulation.     

A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC

A 7-bit Nyquist folding and interpolating analog-to-digital converter (ADC) that converts at 300 MSamples/s is presented. Using current-mode signal processing techniques for analog preprocessing and a front-end sample-and-hold, the proposed 7-bit folding and interpolating ADC yields a wide input bandwidth up to 60 MHz with six effective number of bits. The ADC consumes 200 mW from a 3.3-V power supply. The chip occupies 1.2 mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.     

一种折叠内插式高速模数转换器的设计

描述了一种8bit,125MS/s采样率的折叠内插式ADC采用折叠内插结构设计。系统采用全并行结构的粗量化器实现高3位的量化编码,细量化部分采用折叠内插结构实现低5位的量化编码。电路设计中涉及分布式采样保持电路、折叠内插电路并在文章最后提出一种粗量化修正电路设计。通过HSPICE仿真测试,在采样频率为125MHz下对100M以内的输入频率测试,ADC信噪比达到40.0dB以上,功耗仅为170mW。     

An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique

This paper presents a neural circuit using PWM technique based on an analog-digital merged circuit architecture. Some new PWM circuit techniques are proposed. A bipolar-weighted summation circuit is described which attains 8-bit precision in SPICE simulation at 5 V supply voltage by compensating parasitic capacitance effects. A high performance differential-type latch comparator which can discriminate 1 mV difference at 100 MHz in SPICE simulation is also described. Next, we present a prototype chip fabricated using a 0.6 m CMOS process. The measurement results demonstrate that the overall precision in the weighted summation and the sigmoidal transformation is 5 bits. A neural network has been constructed using the prototype chips, and the experimental results for realizing the XOR function have successfully verified the basic neural operation.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

Design of a single-chip digital lattice equalizer filter

One lattice equalizer stage is designed on a single chip using 4-/spl mu/m NMOS technology. All the arithmetic operations of the chip are performed bit-serially under the control of a global two-phase clock, and they are totally pipelined. The data are represented as 16-bit two's complement fixed-point numbers. A built-in test scheme allows the offline testing of the chip with high fault coverage at a minimal hardware overhead. Direct coupling between chips permits the realization of filters of higher order. In addition, the structure of the lattice equalizer permits the use of the same chip in linear prediction problems. SPICE simulation results and fabrication of the major blocks in the design demonstrated that operating clock frequencies of up to 8 MHz are possible. At the maximum estimated operating clock frequency, the chip can accommodate applications with data rates of up to 500 kHz.     

“The CMOS Inverter” as a Comparator in ADC Designs

This paper introduces a single-ended non-offset-cancelled flash ADC architecture, the Threshold Inverter Quantizer (TIQ). The TIQ is based on a CMOS inverter cell, in which the voltage transfer characteristics (VTC) are changed by systematic transistor sizing. As a result, a significant improvement of speed and reduction of area and power consumption is achieved. A sample TIQ based flash ADC chip including 3-bit, 4-bit and 6-bit versions together has been designed and fabricated with the 2 standard CMOS n-well technology. The proposed ADC cells are suitable for System-on-Chip (SoC) applications in high speed wireless products.     

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.     

嵌入式折叠内插式CMOS模/数转换器设计

基于折叠内插式 ADC结构 ,采用分段式结构、两级折叠、主动内插技术和非线性误差补偿技术 ,采用TSMC0 .35 μm CMOS工艺设计实现了 8位 40 MS/s ADC。基于 BSIM3V3模型 ,采用 Cadence Spectre仿真器对 8位折叠内插式 ADC进行了系统仿真 ,采用 MPW计划对 ADC进行了流片验证 ,仿真和测试结果表明该ADC具有较低的非线性误差和良好的频域特性 ,证明了误差补偿技术的有效性。该 ADC的有效面积为 0 .6mm2 ,适合嵌入式应用。     

一种高速数据采集／重放系统的实现

介绍了一种高速数据采集／重放系统。该系统采用工业控制计算机作为主控设备，在主控计算机内部配置了大容量内存作为高速海量存储介质。系统采用一块基于FPGA的高速信号采集／回放PCI卡来实现。该卡以FPGA为采集／回放的核心控制芯片，并在FPGA内部实现了64位/33MHz的PCI接口逻辑。系统有实时和非实时两种模式，其采集／回放速度高达240MHz，存储容量能扩展至3GB，它可供电磁信号环境仿真及复杂信号分析用。     

A Chip for an Implantable Neural Stimulator

This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation (FES). The purpose of FES is to restore muscular control in disabled patients. The chip performs all the signal processing required in an implanted neural stimulator. The power and digital data transmission to the stimulator passes through a 5 MHz inductive link. From the signals transmitted to the stimulator, the chip is able to generate charge-balanced current pulses with a controllable length up to 256 s and an amplitude up to 2 mA, for stimulation of nerve fibers. The quiescent current consumption of the chip is approx. 650 A at supply voltages of 6–12 V, and its size is 3.9×3.5 mm². It has 4 output channels for use in a multipolar cuff electrode.     

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.     

A DDS Synthesizer with Digital Time Domain Interpolator

A DDS type circuit structure for producing numericallyprogrammable square wave clock signal is presented. The high speed D/Aconverter needed in conventional DDS systems is replaced by an tap delay line time domain interpolator thateffectively increases the sampling rate by a factor of . Thus the circuit can be used up to full clock rate withoutimage filtering. A prototype IC with clock frequency of 30 MHz, 5 bitinterpolator and SFDR of –40 dBc up to 10 MHz and –33 dBcup to 15 MHz has been designed and tested.     

A 1.8 V 15-bit 1 mW 2nd-Order Sigma-Delta Modulator

Low-voltage low-power sigma-delta modulators provide a critical interface in portable mixed-signal electronic systems. This paper deals with the design andimplementation of a low-voltage, low-power 2nd-ordersigma-delta modulator operating from a single 1.8 V powersupply using a conventional 3.3 V, double-poly, 0.35 mCMOS process, based on fully-differentialswitched-capacitor techniques. All the circuit blocks areintegrated on one chip, and the input common-mode voltageis set at mid-rail, resulting in low power dissipation,minimum off-chip components, and high efficiency,flexibility and compatibility. The design is useful forvoice applications in personal communications systemssupplied by two nickel-cadmium or alkaline batteries. Themodulator exhibits a 15-bit dynamic range for a 7 kHzbandwidth, and a 14-bit dynamic range for a 20 kHzbandwidth at an oversampling frequency of 2.56 MHz. Thepeak SNDR reaches 62 dB. The complete 2nd-order modulatorhas a power dissipation of 0.99 mW, and occupies 0.31mm² die area excluding bonding pads.     

16通道恒流LED驱动芯片的PWM调光功能设计

介绍了一种应用于多通道恒流LED驱动芯片的PWM调光功能的实现方案,通过脉宽调制来改变流过各个通道LED的平均电流,进而实现了LED的调光控制。该模块由128 b串行移位寄存器,8 b数据锁存器,8 b计数器,以及8 b PWM灰度比较器构成,输出具有256阶灰度调节功能的PWM控制信号。外部数据时钟采用25 MHz,内部振荡器采用1.2 MHz。整体功能由Verilog HDL语言编程实现。     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

A 10000 frames/s CMOS digital pixel sensor

A 352×288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-μm CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4×9.4 μm with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 μV/e^-. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization