Shape-VQ-based lossless hybrid ADPCM/DCT coder

The discrete cosine transform (DCT) has been shown as an optimum encoder for sharp edges in an image (Andrew and Ogunbona, 1997). A conventional lossless coder employing differential pulse code modulation (DPCM) suffers from significant deficiencies in regions of discontinuity, because the simple model cannot capture the edge information. This problem can be partially solved by partitioning the image into blocks that are supposedly statistically stationary. A hybrid lossless adaptive DPCM (ADPCM)/DCT coder is presented, in which the edge blocks are encoded with DCT, and ADPCM is used for the non-edge blocks. The proposed scheme divides each input image into small blocks and classifies them, using shape vector quantisation (VQ), as either edge or smooth. The edge blocks are further vector quantised, and the side information of the coefficient matrix is saved through the shape-VQ index. Evaluation of the compression performance of the proposed method reveals its superiority over other lossless coders     

Overview and performance of CCITT/ANSI embedded ADPCM algorithms

Embedded adaptive differential pulse coded modulation (ADPCM) algorithms quantize the differences between the input signal and the estimated signal into core bits and enhancement bits. CCITT Recommendation G.727, which describes embedded ADPCM encoding algorithms with 5, 4, 3, and 2 core bits, is virtually identical to the corresponding ANSI standard T1.310. The main features of G.727 and T1.310 and performance results are presented. A formal subjective evaluation of the speech performance of embedded ADPCM algorithms indicates that a midrise quantizer provides better voice transmission performance than its midtread counterpart when two core bits are used. The subjective data also show that the performance of the 40-kb/s midrise ADPCM algorithm with two feedback bits is indistinguishable from that of 64-kb/s pulse code modulation (PCM) for up to four tandem encodings. Embedded algorithms are therefore recommended for flexible congestion control of integrated traffic in multinode networks     

Improved embedded zerotree wavelet coder

An improved embedded zerotree wavelet (IEZW) is presented, which can significantly reduce the scanning and symbol redundancy of the existing EZW     

An embedded still image coder with rate-distortion optimization

It is well known that the fixed rate coder achieves optimality when all coefficients are coded with the same rate-distortion (R-D) slope. In this paper, we show that the performance of the embedded coder can be optimized in a rate-distortion sense by coding the coefficients with decreasing R-D slope. We denote such a coding strategy as rate-distortion optimized embedding (RDE). RDE allocates the available coding bits first to the coefficient with the steepest R-D slope, i.e., the largest distortion decrease per coding bit. The resultant coding bitstream can be truncated at any point and still maintain an optimal R-D performance. To avoid the overhead of coding order transmission, we use the expected R-D slope, which can be calculated from the coded bits and is available in both the encoder and the decoder. With the probability estimation table of the QM-coder, the calculation of the R-D slope can be just a lookup table operation. Experimental results show that the rate-distortion optimization significantly improves the coding efficiency in a wide bit rate range.     

ADPCM语音编解码电路设计及FPGA实现

近年来，多媒体技术逐渐深入到人们的生活中。MP3播放器已经成为流行的便携式音频播放设备，由于MP3编码算法非常复杂，目前，一部分MP3播放器的录音功能主要基于ADPCM算法和DSP来实现。本文阐述了ADPCM语音编解码VLSI芯片的设计方法以及利用FPGA的硬件实现。     

An improved wavelet-based image coder for embedded greyscale and colour image compression

The embedded zero-tree wavelet (EZW) coding algorithm is a very effective technique for low bitrate still image compression. In this paper, an improved EZW algorithm is proposed to achieve a high compression performance in terms of PSNR and bitrate for lossy and lossless image compression, respectively. To reduce the number of zerotrees, the scanning and symbol redundancy of the existing EZW; the proposed method is based on the use of a new significant symbol map which is represented in a more efficient way. Furthermore, we develop a new EZW-based schemes for achieving a scalable colour image coding by exploiting efficiently the interdependency of colour planes. Numerical results demonstrate a significant superiority of our scheme over the conventional EZW and other improved EZW schemes with respect to both objective and subjective criteria for lossy and lossless compression applications of greyscale and colour images.     

高性能低功率turbo编码器IP核

它可提供1Mbit/s的吞吐量,时钟频率仅为8.2MHz时执行1.5GOPS,在1.5dB信噪比时位误码率达10~(-6)     

基于FPGA技术的曼彻斯特编码器设计

曼彻斯特码是一种性能优良的数字基带信号传输码,具有消除直流成分,隐含时钟等特性,使得他在石油勘探测井中有着广泛的应用。从曼彻斯特码的帧结构出发,在阐明曼彻斯特码基本工作原理的基础上,应用FPGA技术,利用硬件描述语言VHDL设计完成曼彻斯特编码器,所设计的系统包含使能、复位、同步字的产生以及奇校验等功能,所编写的VHDL源程序经Altera公司的软件Max PlusⅡ进行调试、优化及仿真,仿真结果与理论分析完全吻合。     

Design and simulation of an efficient adaptive delta modulationembedded coder

An embedded coding version of hybrid companding delta modulation (HCDM) is described that operates from 16 to 48 kb/s in 8 kb/s steps. The embedded HCDM coder employs the explicit noise coding technique to transmit an adaptive PCM (APCM) coded version of the HCDM reconstruction error signal as a supplementary bit stream that may be partly or wholly deleted in transmission. SNR performance with speech input depends critically on the design of the supplemental APCM code and two new coding algorithms are investigated. In algorithm 1, the basic cue for step size adaptation is obtained from the RMS slope energy of the HCDM output whereas in algorithm 2, the HCDM reconstruction error is logarithmically compressed before quantisation and the basic step size is derived from peak input magnitudes. Instantaneous adaptation for both algorithms is achieved by using step size multipliers which are optimised for operation at single fixed bit rates and also for decoding with an unknown number of input bit deletions. Simulation results show that SNR performance is significantly enhanced using either algorithm and a graceful reduction of reconstructed speech quality with progressive bit deletion is achieved over the range from 48 kb/s to 16 kb/s. On the whole, the SNR performance of the embedded HCDM system is superior in comparison with conventional HCDM     

基于EDA技术的HDB3编码器的设计与实现

HDB3码是数字基带通信系统中重要组成部分之一,因其具有无直流成份,检错能力强,具有时钟恢复性能等优点,成为ITU推荐使用的基带传输码型之一。首先介绍了HDB3编码的原理和方法,提出了一种基于EDA技术实现的HDB3编码器的方法,具有电路简单,成本低,开发周期短,执行速度高,升级方便等特点。     

基于ADPCM算法的汽车智能语音报警系统的设计

介绍了一种采用FPGA硬件实现ADPCM算法的方法,并基于此算法对预先采集的各种报警语音进行压缩编码并存储.在遇到危险时,由单片机做出危险判断,并自动选择播放相应的报警语音以提示驾驶员及时采取措施.     

60路32kb／s ADPCM转换器的大规模集成电路设计

３２ｋｂ／ｓ ＡＤＰＣＭ转换设备的研制在数字通信领域具有显著的社会与经济效益。本文的工作是在用中小规模集成块构成了６０路转换编译码系统样机的基础上，进行了大规模专用集成电路芯片的电路设计，拟用两片５０００门门阵列实现全系统集成，目前，线路级的设计已经完成，并且成功地通过了Ｄａｉｓｙ工作站的计算机逻辑模拟。     

使用系统总线性能计数器来测量和改善嵌入式系统的性能

了解系统总线的活动情况可帮助开发工程师显著改善嵌入式应用的性能。过去,由于嵌入式处理器缺乏复杂的软硬件结合特性,因此监测系统总线的活动情况是一项挑战性难题。在系统级了解应用程序的行为对于有效利用系统资源非常关键,这些资源包括外部存储器、DMA控制器、仲裁、系统总线互连等。     

基于ARM的嵌入式汽车检测装置的设计与实现

结合基于ARM的嵌入式汽车安全性能检测装置的设计，对整个嵌入式系统开发过程，包括硬件平台，操作系统的选择，开发环境与开发工具以及软／硬件的协同设计方法进行了探讨。     

一种嵌入式系统设计与应用

嵌入式操作系统具有面向特定应用的特点,各种应用千差万别,这决定了不太可能出现可普遍适用的嵌入式实时操作系统。因此,开发、升级具有自主知识产权的嵌入式实时操作系统是很有意义的。本文首先介绍了嵌入式系统的结构和发展趋势;接着针对C8051F120单片机进行了简单介绍,并在其上实现μC/OSⅡ操作系统的移植,最后对加载了EPA协议栈的操作系统进行了测试,通过测试成功地验证了该系统的稳定性和可靠性。     

32kb／sADPCM中高速乘法器的设计

本文介绍了６０路３２ｋｂ／ｓＡＤＰＣＭ专用芯片中的高速乘法器的逻辑设计和提高运算速度的方法。通过优化设计，该乘法器运算速度高，电路简单，对芯片制造工艺要求不高。     

Design of a pitch synchronous innovation CELP coder for mobilecommunications

This paper describes the design of a speech coder called pitch synchronous innovation CELP (PSI-CELP) for low hit-rate mobile communications. PSI-CELP is based on CELP, but has more adaptive excitation structures. In voiced frames, instead of conventional random excitation vectors, PSI-CELP converts even the random excitation vectors to have pitch periodicity by repeating stored random vectors as well as by using an adaptive codebook, in silent, unvoiced, and transient frames, the coder stops using the adaptive codebook and switches to fixed random codebooks. The PSI-CELP coder also implements novel structures and techniques: an FIR-type perceptual weighting filter using unquantized LPC parameters, a random codebook with a conjugate structure trained to be robust against channel errors, codebook search with delayed decision, a gain quantization with sloped amplitude, and a moving average prediction coding of LSP parameters, Our speech coder is implemented by DSP chips. Its coded speech quality at 3.6 kb/s with 2.0 kb/s redundancy is comparable to that of the Japanese full-rate VSELP coder at 6.7 kb/s with 4.5 kb/s redundancy. The basic structure of this PSI-CELP coder has been chosen as the Japanese half-rate speech codec for digital cellular telecommunications     

The Design of an ADPCM/TASI System for PCM Speech Compression

This paper describes the design of a digital speech interpolation (DSI) system called ADPCM/TASI for adaptive differential PCM with time assignment speech interpolation. This system is designed to compress the output of two T1 24-channel PCM carrier terminals into a 1.544 Mbit/s signal that can be transmitted over a single T1 carrier line. The design is based on a bit slice microprocessor structure. Alternative designs are also described.     

基于单片机的HDB3编/译码器的设计与实现

介绍了一种基于单片机的HDB3编/译码器的设计.以常用的51系列单片机为核心,结合外围电路,实现了HDB3编/译码器的功能.在单片机应用系统之间的数字基带通信中,具有一定的应用前景.     

用L9320实现ADPCM语音编解码

L9320是LANWAVE公司推出的一款自适应音频脉冲编码 (ADPCM)编解码器。该器件除具有正常的ADPCM编码解码模式外 ,还有PCM编解码模式、电源测试模式以及编解码器测试模式。文中主要对L9320编解码器的工作原理和使用方法进行了分析,给出了L9320在便携式语音系统中的典型应用电路