CDMA与LTE-FDD室内覆盖混合组网探讨

主要针对2100MHz频段内10MHz带宽的LTE-FDD在多种室内场景下的链路预算、单天线的覆盖能力进行了分析.在此基础上,给出了单通道及双通道模式下LTE-FDD和CDMA室内分布系统共建的建设方案.     

基于ADS6122和FPGA的多通道信号采集系统的设计

针对超声成像系统的信号采集要求,介绍了一种基于FPGA的多通道数据采集和传输系统的设计与实现。采用ADS6122,实现了12 bit、单通道最高采样频率达65 MHz的A/D转换电路。该系统采用FPGA进行逻辑控制,实现了高频信号单通道采集,低频信号多通道同时采集的数据采集系统。系统测试结果表明:当单通道模拟信号输入频率不超过7 MHz时,得到的采样速度和采样精度都能满足超声信号采集的高要求。该系统还可以作为相关多通道信号采集系统设计的参考。     

记忆体明日之星系列(三)——同步DRAM架构剖析

发展缘起 CPU的快速发展,内部速度达66MHz的比比皆是,且不断在提升当中,高端的CPU,已达200MHz,而且300MHz的也已上市,这些高端CPU,皆具64位元暂存器与汇流排,数据处理速度达1200MIPS。如图1所示为CPU所需频宽及DRAM记忆     

双核3U Compact PCI服务器级工业计算机

cPCI-3920搭配英特尔Core2Duo双核处理器,具有4MB闪存（Cache）与667MHz总线,若客户需要更省电与更佳的散热能力,也可选择搭配极低功耗的单核Celeron处理器。cPCI—3920支持具备纠错功能（ECC）的单通道DDR2—400SDRAM,最高容量达2GB,内存同样也是直接焊接在PCB板上,具有极佳抗震性。     

基于矩阵架构的大规模平行处理器

适用于图像和音频多媒体数据处理的基于矩阵架构的大规模平行处理器具有紧凑的2048个处理单元和1Mb SRAM，可以在200MHz的时钟频率下实现每秒运行10亿次的性能。     

吉时利推出8×8MIMO测试系统

美国吉时利仪器公司日前推出业界第一款测量级8×8MIMO系统。该测试系统是适用于技术研究和产品开发的最先进的高性能MIMO测试平台,能够轻松测试极其复杂的信号和通信架构。吉时利MIMO射频测试系统包括频率范围达400MHz到6GHz的2820型射频矢量信号分析仪（VSA）、能够产生10MHz到6GHz频率范围信号的2920型射频矢量信号发生器（VSG）、提供了用于分析单通道到最高4×4MIMO配置的多通道射频设备各种测量套件的280111型WLAN802．11n信号分析软件、     

基于脉动阵列的复数定点QR分解VLSI设计

提出一种应用Givens变换实现QR分解的脉动阵列中的边界单元和内部单元电路结构。在硬件成本增加不多的条件下,应用牛顿-拉夫逊迭代方法和查询表技术,实现了平方根倒数的快速计算。综合的电路工作时钟达100MHz,两种单元的数据处理周期均为120ns,阵列数据处理速度高于相关文献报道40%以上。     

超级计算机到桌面

每秒浮点运算超过10亿次的计算机通常被称为“超级计算机”,苹果电脑公司的PowerMacG4是世界上首批具有超级计算能力的桌面个人电脑。苹果PowerMacG4系列产品采用由苹果、Motorola和IBM联合开发的最新一代PowerPCG4中央处理器,主频速度高达400MHz、450MHz或500MHz,先进的“极速引擎”矢量处理技术集成了162个SIMP(单指令多数据)指令,全128位内部内存数据通道提供了目前全球独一无二的128位数据处理能力。来自第三方权威测试结果表明,在运行包括AdobePhotoshop在内的专业应用软件时,PowerPCG4的速度超过800MHzPentiumⅢ芯片50%…     

低中频接收机中高线性度正交混频器设计

本文首先以Gilbert单元为核心,利用折叠结构,设计了一种具有高线性度的CMOS单通道混频器。该混频器的输入射频信号设用了600MHz、输出中频为8MHz。接着本文应用这一混频器设计了低中频接收机中所需的双通道正交混频器。经仿真得到其在3.3V的电源电压下,转换增益为8.4dB,输入1dB压缩点和IIP3分别达到0dBm和10dBm,单边带噪声系数为16.8dB。     

快速数据采集——由凌力尔特公司的高性能模拟解决方案

当需要对频率范围为几Hz至几MHz的模拟信号进行快速数字化处理时，对于众多的应用来说，逐次逼近寄存器（SAR） ADC是上佳的选择。其快速响应和低延迟使得SAR ADC成为单通道或多通道数据采集的理想选择。SAR ADC具有许多的特点和好处。     

基于AD9959的四通道高频信号源研制

设计了一种以直接数字频率合成（DDS）芯片为核心的四通道高频信号源,每通道均可独立输出1 Hz～200MHz的高频正弦波信号,输出幅度范围为1mVpp～4Vpp,谐波失真小于等于5%,且通道之间相位均独立可调。介绍了AD9959芯片的主要功能,给出了信号处理电路的设计及PCB板的电磁兼容设计。信号源经实际测试,输出频率范围、输出幅度范围和通道间相位调节等技术指标均达到设计要求。     

一种四通道PMC宽带数字接收机的设计与实现

介绍了一种通用宽带四通道数字接收机PMC背板的设计与实现.该设计用ADI公司的AD6645(14 bit,80 Msam-pie·s-1/105 Msample·s-1)作为模数转换器件,采用专用DDC芯片ISL5416和StratixⅡ系列的FPGA级联的结构,用PCI9656作为PCI接口芯片,板卡为标准PMC板型.文中给出了板卡的原理结构和性能指标的测试结果等.实践表明,该数字接收机具有精度高、使用灵活、处理和互联能力强等优点.     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.     

A High Speed VLSI Architecture for Handwriting Recognition

This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC.HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).     

通用数字电路板测试系统硬件设计

针对传统依靠人工使用示波器、万用表、逻辑分析仪等设备对数字电路板进行测试具有过程复杂、工作量大、可靠性低等缺点,介绍一套通用数字电路板测试系统的硬件设计方案。跟传统数字电路板测试系统相比,文中的设计性能参数更优,主要包括:测试频率最高50 MHz并可调为100 MHz的整数分频;测试电平兼容-6~+9 V且可编程步长为100 mV;测试通道32路,每通道可设为输入输出三态可选且同步工作,存储深度1 Mbit,电流驱动能力达50 mA并有过载保护。     

GaAs ICs for high-speed signal processing

A complete family of small-scale integration (SSI) and middle-scale integration (MSI) analog and digital GaAs ICs for real-time signal processing is reported. These circuits have been used on several microstrip PC board applications with clock frequencies ranging from 500 MHz to 1 GHz. Detailed circuit performances and future trends are presented and discussed     

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

基于光电倍增管的低噪声前置放大器的设计及其信号处理

利用低噪声前置运算放大器把光电倍增管的输出信号尽可能无噪声的放大。从运放的选择,多级放大电路的设计要点,放大电路的噪声估算,PCB板布局连线和屏蔽等方面,提出了实用化的带宽达10 MHz的电路设计形式,以及注意事项及其信号调理方法。仿真结果显示了所设计电路的信号放大情况,此电路设计形式可以很好的放大并处理光电倍增管的输出信号。     

一种新的收发一体机结构

介绍了一种将接收机和发射机两种功能模块整合的收发一体机结构.采用了提出的Transformer信号耦合结构,使收发两路逆行信号共用一路放大器、滤波器、本振,只需配置两个分别用于上、下变频的混频器,在MCU控制下即可实现接收和发射两项功能.成功制造出了用于140MHz中频和10MHz基带信号之间的收发一体机,经测试功能得到完全实现,且性能良好,能有效地简化系统、降低成本、减小电路板面积,有很大应用价值.     

Design and Implementation of Subspace-Based Speech Enhancement Under In-Car Noisy Environments

In this paper, a new subspace-based speech enhancement model is presented for in-car speech enhancement. To effectively suppress background noise, this model incorporates a perceptual filterbank and an auditory gain adaptation derived from a psychoacoustic model into a signal subspace approach. The projection approximation subspace tracking deflation (PASTd) algorithm is used to track the signal subspace. For real-time processing, a system-on-a-programmable-chip architecture and a very large scale integration design of the PASTd algorithm are proposed. To realize a pipeline computation, this paper presents a pipelined PASTd architecture without data-dependent hazards. The maximum clock rate is 9.7 MHz, and the typical clock rate, which achieves the real-time requirement, is 4.6 MHz. The corresponding architecture was experimentally verified via an ALTERA EPXA10 development board.