The tapered matrix amplifier: a low-power high-gain broadband amplifier

A new distributed amplifier topology that offers greatly reduced power consumption is presented. The tapered matrix amplifier (TMA) originates from the combination of transmission line tapering and matrix cascading of distributed amplifiers. The design of a TMA is however complicated by contrasting requirements of the tapered lines, the lumped line approximation and the parasitics of the circuit components. Therefore, a pragmatic design approach leveraging circuit optimization is proposed to handle these complexities. As a proof of concept, a prototype broadband amplifier was implemented in a 90 nm bulk CMOS process. It features an average gain of 15.8 dB over the pass-band, stretching from DC to 22 GHz, while consuming only 12.9 mW of DC power. The average noise figure in the pass-band is 5.4 dB, and the average IIP3 is ?7.3 dBm. The die area occupied by the amplifier is only 0.31 mm². In addition, it is shown that the prototype design can be easily adapted for high linearity while keeping the increase in power consumption to a minimum.     

Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier

We present the design of two wide-band, low-power and low-noise amplifiers (LNAs) using SiGe BiCMOS technology. The distributed LNA demonstrated 0.1-23-GHz bandwidth and 14.5-dB gain with less than /spl plusmn/1-dB gain flatness. It exhibited 5-dB noise figure and 14.8-dBm output IP3, and dissipated 54-mW dc power. Comparable circuit performance was also obtained in the lumped LNA while utilizing only one-fifth the chip area of the distributed LNA.     

A BiCMOS low-power current mode gate

A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML     

BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network

A new image sensor is presented that comprises a chopper-stabilised edge detector and a correlated-double-sampling readout circuit, based on 2 mu m BiCMOS technology for pattern recognition neural network VLSI applications operating at 77 K. With the chopper-stabilised edge detector and the correlated-double-sampling readout technique, the two-dimensional photodiode array, which can be efficiently built with only one readout circuit, provides a bidirectional edge detection capability for high resolution image sensing applications operating at 77 K.<>     

A compact low-power BiCMOS log-domain filter

A third-order Chebyshev filter based on the log-domain principle and integrated in a 1-μm BiCMOS process is presented. It has a nominal cutoff frequency of 320 kHz corresponding to a bias current of 1 μA, and can be frequency tuned over almost three decades up to about 10 MHz. It operates with a nominal supply voltage of 1.2 V, maintaining a dynamic range (DR) at 1% THD of 57 dB. For cutoff frequencies in the range of 10 kHz, the supply voltage can be reduced down to 0.9 V. The filter occupies an active area of 0.25 mm² and dissipates 23 μW, corresponding to a power consumption per pole and edge frequency of only 24 pJ. These results demonstrate the potential of log-domain filters for very low-voltage and low-power applications     

MOS-C single amplifier biquads using the operational transresistance amplifier

A configuration for the realization of voltage-mode second-order filters employing a single operational transresistance amplifier (OTRA) as the active element is presented. This topology can synthesize lowpass, highpass, bandpass, notch and allpass filtering functions. The presented filters are suitable for MOS-C implementation, yielding the filter parameters to be electronically tunable. Theoretical analysis is verified with PSPICE simulation.     

一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

Two-stage high-gain optical amplifier

A two-stage semiconductor optical amplifier is discussed. Net fiber-to-fiber gains as high as 36.5 dB have been achieved. When used in a fiber-optic transmission system, using a commercial 1.7 Gb/s regenerator, the fiber span between transmitter and regenerator is increased to 151 km and 1.3 μm wavelength. With a 1.55 μm two-stage amplifier, a transmission distance of 180 km at 3.4 Gb/s is demonstrated     

A high-gain monolithic D-band InP HEMT amplifier

This paper describes a three-stage monolithic amplifier that exhibits a small-signal gain of 30 dB at 140 GHz. The amplifier employs AlInAs/GaInAs/InP high electron mobility transistor devices with 0.1×150 μm² gate periphery, is implemented with coplanar waveguide circuitry fabricated on an InP substrate, and occupies a total area of 2 mm². Gain exceeding 10 dB was measured on-wafer from 129 to 157 GHz. This is the highest reported gain per stage for a transistor amplifier operating at these frequencies     

A high-performance, low-power complementary coupled BiCMOS circuit

Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits     

A low-power BiCMOS switched-capacitor filter for audio codecapplications

A fully integrated fourth-order filter embedded in a complete 16-b oversampled D/A converter to be used in an audio stereo codec is presented. The possible noise and distortion sources have been accurately evaluated in the design and their contributions have been properly limited. This allows the reduction of the power consumption while satisfying the application requirements. The filter is realized in 0.7-μm BiCMOS technology with an active area of about 1.3 mm² . A total harmonic distortion (THD) of -75 dB for a full scale input signal and an SNR of 96 dB have been achieved. The power consumption of the filter has been maintained within about 40 mW from a single 5-V supply voltage     

A 12-dB high-gain monolithic distributed amplifier

By reducing gate and drain line loss associated with the active elements of a distributed amplifier, significant gain improvements are possible. Loss reduction is achieved in a novel monolithic distributed amplifier by replacing the common-source FET's of the conventional design with cascode elements having a gate length of one-quarter micron. A record gain of over 10 dB from 2 to 18 GHz and a noise figure of 4 dB at 7 GHz have been achieved on a working amplifier. Details of the design and fabrication process are described.     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

A low-noise BiCMOS amplifier channel for telecommunications

A low-noise low-pass amplifier channel designed for telecommunications is described. The channel has an 80-kHz corner frequency and total dynamic range of 94 dB. To achieve the high dynamic range, the amplifier channel is constructed with a BiCMOS process and a relative high supply voltage of ±8V is used. To further increase the dynamic range, the baseband amplifier has two branches, a low gain (A = 29 dB) and a high gain (A = 73 dB) branch, comprising a common continuous-time preamplifier and separate antialias filters, switchedcapacitor filters, and postamplifiers. Differential signal processing is used to reduce the effect of common-mode disturbances.     

低功耗CMOS限幅放大器设计

利用0.18μm CMOS工艺设计了应用于光接收机中的10Gb/s限幅放大器.此限幅放大器由输入缓冲,4级放大单元,一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路构成.输入动态范围为38dB(10mV～800mV),负载上的输出限幅在400mV,在3.3V电源电压下,功耗仅为99mW.整个芯片面积为0.8×1.3mm2.     

A wideband low-noise variable-gain BiCMOS transimpedance amplifier

A new monolithic variable gain transimpedance amplifier is described. The circuit is realized in BiCMOS technology and has measured gain of 98 kΩ, bandwidth of 128 MHz, input noise current spectral density of 1.17 pA/√(Hz) and input signal-current handling capability of 3 mA     

A high-gain GaAs amplifier with an AGC Function

A high-gain amplifier consisting of three GaAs monolithic IC chips, a preamplifier, an automatic gain control (AGC) amplifier, and a postamplifier, is developed. The fabricated low-noise low-VSWR amplifier has a 45-dB gain, a 13-dB AGC range, and a 1.6-GHz bandwidth with a power consumption of 2.5 W. It is a promising candidate for use in high-speed data rate transmission systems.