Pseudorandom BIST for test and characterization of linear and nonlinear MEMS

In this paper we study the use of the pseudorandom (PR) technique for test and characterization of linear and nonlinear devices, in particular for micro electro mechanical systems (MEMS). The PR test technique leads to a digital built-in-self-test (BIST) technique that is accurate in the presence of parametric variations, noise tolerant, and has high-quality test metrics. We will describe the use of the PR test technique for testing linear and nonlinear MEMS, where impulse response samples of the device under test are considered to verify its functionality. Next, we illustrate and evaluate the application of this technique for linear and nonlinear MEMS characterization.     

面向功耗优化的伪随机测试矢量生成

随着集成电路设计复杂度和工艺复杂度的提高，集成电路的测试面临越来越多的挑战，内建自测试作为一种新的可测性设计方法，能显著提高电路中随机逻辑的可测性，解决一系列测试难题，但它同时也引起了测试功耗问题，本文提出了一种面向功耗优化的伪随机测试向量生成方法，在保证故障覆盖率的条件下，大大降低了测试功耗。     

Online Testing of MEMS Based on Encoded Stimulus Superposition

This article presents a technique that enables online testing of sensors through the superposition of the test stimulus onto the measurand. Perturbations due to the surrounding environment can very often introduce fluctuations in the test output creating a major concern for this type of sensor testing. In this paper, a signal processing technique is proposed where the test stimulus is encoded by a pseudo-random sequence in order to reduce the test output fluctuations. The trade-off between the level of rejection of a perturbation and the overall test time is studied. In the case of the MEMS accelerometer considered in this paper, it is theoretically demonstrated that the rejection is more than 20 dB for a test time of 2.55 s. Furthermore, excessively strong perturbations can be monitored so that the test status is updated only if the accuracy of the test signal permits so. The technique has been implemented on a demonstration board and validated on a vibration platform.

Generation of Electrically Induced Stimuli for MEMS Self-Test

A major task for the implementation of Built-In-Self-Test (BIST) strategies for MEMS is the generation of the test stimuli. These devices can work in different energy domains and are thus designed to sense signals which are generally not electrical. In this work, we describe, for different types of MEMS, how the required non-electrical test stimuli can be induced on-chip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The on-chip test signal generation is illustrated for the case of MEMS transducers which exploit such physical principles as time-varying electrostatic capacitance, piezo-resistivity effect and Seebeck effect. These principles are used in devices such as accelerometers, infrared imagers, pressure sensors or tactile sensors. For implementation, we have used two major MEMS technologies including CMOS-compatible bulk micromachining and surface micromachining. We illustrate the ability to generate on-chip test stimuli and to implement a self-test strategy for the case of a complete application. This corresponds to an infrared imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a suspended membrane that contains several thermopiles along the different support arms. The on-chip test signal generation proposed requires only slight modifications and allows a production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.     

MEMS动态测试技术

阐述了基于频闪成像、计算机视觉和干涉测量的MEMS动态测试技术、基于激光多普勒测振的MEMS动态测试技术以及基于其他原理和方法的MEMS动态测试技术等的测试原理、测试方法与研究现状,指出了MEMS动态测试技术进一步的研究方向。     

Electro-thermal Stimuli for MEMS Testing in FSBM Technology

The development of low-cost go/no-go procedures for MEMS production testing is one of the main issues of MEMS manufacturability. In particular, the generation of low-cost test stimuli is a real challenge. In this paper, we investigate the generation of electrically-induced thermal stimuli to test electro-mechanical structures. Static, transient and harmonic responses are studied and it is demonstrated that they can be used for efficient detection and classification of several faulty devices.     

一种基于模糊熵的混沌伪随机序列复杂度分析方法

该文将模糊理论引入到混沌伪随机序列复杂度测度中,构造了用于序列复杂度测度的模糊隶属函数,并在此基础上研究了一种新的基于模糊熵(Fuzzy Entropy, FuzzyEn)的混沌伪随机序列复杂度测度。仿真结果表明,与现有主要的混沌伪随机序列复杂度测度方法相比较,FuzzyEn测度不仅能够有效地测度出不同复杂度的混沌伪随机序列,而且具有更加好的对序列符号空间的适用性,更加小的对测量维度的敏感性以及更强的对分辨率的鲁棒性。     

EL6249C及其在MEMS动态测试中的运用

EL6249C是美国Elantec半导体公司推出的四通道激光二极管电流放大器。文中根据频闪成像原理 ,利用EL6249C设计了一套频闪驱动电路 ,该驱动电路可驱动高亮LED ,以产生MEMS动态测试中所需的频闪光 ,为后续MEMS器件的动态特性提取和分析做准备。     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

Built-in Self Test Based on Multiple On-Chip Signature Checking

We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The proposed test architecture reduces detection latency and eliminates the lengthy scan-out phase from each test session by allowing testing and on-chip signature comparison of multiple intermediate signatures to occur concurrently. The work is based on a novel procedure to implement the multiple on-chip signature checking. We show that such a test method gives significant improvements in test application time and aliasing probability. This paper also presented two techniques to minimize the test area overhead with a very small test time overhead compare to the conventional schemes. These techniques resulted in up to 80% savings in test area overhead for some High-level synthesis benchmark circuits. This paper also presents an aliasing analysis of the proposed scheme.     

多周期伪随机序列扩散体近场接收点的优化选择

在远场条件下,伪随机序列扩散体具有良好的扩散特性。多周期的伪随机序列扩散体越来越多地应用在各种小型房间里,接收点到多周期伪随机序列扩散体的距离并不满足远场条件。根据基尔霍夫衍射理论,研究了扩散频率范围内接收点在近场时多周期伪随机序列扩散体的极性响应,并与平板进行了比较和分析,总结出表征扩散性能变化的过渡距离。实际使用时要适当选择接收点距离,使既能获得良好的扩散效果,又能保证一定的声压级。     

MEMS高温电容式压力传感器的研制与测试

介绍了一种用硅-硅键合MEMS技术制作的高温电容式压力传感器,并给出了详细的制作工艺.文中对测试装置、测试电路进行了介绍和深入分析,最后用此测试电路对制作的传感器器件进行了高温测试,测试结果表明这种微传感器可在低于350℃的条件下正常工作,且具有很大的线性工作范围、良好的稳定性和较高的灵敏度,其应用前景十分广阔.     

Built-in-self-test techniques for MEMS

As predicted by technology roadmaps, embedded micro-electro-mechanical-systems (MEMS) is yet another step in the continuous search for higher levels of integration and miniaturization. MEMS are analog components and the test paradigm is similar to the case of analog and mixed-signal circuits. However, given the fact that they work with signals other than electrical, the test of these embedded parts poses new challenges. In this paper, we will review some recent works in this field and we will present a complete approach to MEMS built-in-self-test (BIST) based on pseudorandom testing.     

MEMS薄膜泊松比测试方法的研究进展

综述了MEMS薄膜泊松比的测试方法,简述了测试薄膜泊松比的目的和意义。结合测试环境与测试手段详细地列举了几类常用的测试方法:拉伸法、纳米压痕法、鼓膜法、谐振法、弯曲法和扭转变形法,介绍了各种测试方法的发展过程,并分析了各种测试方法在使用中所面临的关键问题。最后,从可操作性、精确度和适用范围等方面比较了各种方法的优劣,给出了测试方法选取的建议,并对MEMS薄膜测试技术的发展进行了展望,指出在线测试技术将推动MEMS薄膜测试技术的进一步发展。     

单电容式及差分电容式HEMS传感器检测系统

传感器技术是信息社会的四大支柱之一,传感器和计算机结合形成的智能系统大大的拓展了人类生活的空间.在传感器家族中,根据电容的物理特性制作的传感器占有重要地位.电容传感器是很好的状态传感器,可提高电容检测,尤其是微小电容检测的精度,是目前测控技术的热点.本文重点介绍一套微小电容差分高精度检测电路,该套电路可测物体的运动加速度,加速度计的分辨率可达2-18.     

MEMS可靠性技术

MEMS的可靠性是其能否成功应用的一个关键。本文对MEMS可靠性测试的要求与可靠性测试系统ShiMMeR进行了分析,通过对MEMS的可靠性实验与失效模型的综述,对MEMS的可靠性设计进行了探讨。     

伪随机序列调制信号的多普勒频移估计

讨论了伪随机序列调制信息的多普勒频移和延迟的估计问题。隐藏在非透光残骸内的慢速运动目标反射信号含有周期信息。例如,这些信息可能是由人为或自然灾害后幸存人员的呼吸和心跳引起的。非相关与相关噪声都会导致编码序列薄结构出现误差。提出了一种拥有非相干鉴频器的准最优接收机。该接收机拥有两个相位同步的平行通道。主要讨论了该接收机合成过程的工作条件及其特性。这一合成过程建立在改进的非线性滤波过程基础之上。整个合成过程分为两步:第一步假设信号频率无频移且已掌握该信号处理算法的基本结构;第二步,假设该算法结构未改变,利用信号滤波理论设计了移频控制回路中的滤波器。频移与信号延迟的联合估计序列可用作动态卡尔曼滤波器模型。     

全光伪随机码倍速关键技术

提出了基于太赫兹光非对称解复用器(TOAD)结构来实现全光伪随机码(PRBS)倍速中全光波长变换及全光或逻辑运算两项关键技术的方案。对TOAD结构的开关特性进行了理论与实验研究,并利用TOAD结构实现了10Gb/s速率的波长变换和全光或逻辑的仿真与实验。结果表明:继续减小控制脉冲宽度和开关窗口宽度,利用TOAD结构可以获得更高速率的波长变换和全光或逻辑运算;利用这两项关键技术,基于TOAD结构可实现PRBS倍速,获得更高速率的全光PRBS码流。     

Test and Testability of a Monolithic MEMS for Magnetic Field Sensing

This paper addresses MEMS testing through a case study: a micromachined magnetic field sensor with on-chip electronics. The sensor element is based on a cantilever beam that is deflected by means of the Lorentz force. Embedded piezoresistors are used to detect strain in the cantilever beam and thus to detect the magnetic field. A test approach is presented for the whole system focussing on fault classification, on design for testability and on production test costs. Fault classification introduces several catastrophic and parametric faults on both mechanical and electrical elements. Simple and low-cost design for testability such as test point insertion is then discussed for test cost reduction and for fault coverage enhancement.     

On-Chip Weighted Random Patterns

Even though there has been a considerable effort in proposing weighted random pattern testing schemes over the years, insufficient attention has been devoted to their implementation. This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to go after the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.