线性电路K故障诊断法的有效范围

在使用K故障诊断法时,为提高电路的可诊断性,可以采取诸如增加可及节点,或改变激励点,增加激励和测量次数等办法。本文对这些措施的有效性,以及如何增加可及节点问题进行了详细的讨论,特别着重对比较有效的多激励法进行研究,给出了用多激励法进行诊断时,电路可K故障支路诊断的条件。     

容差网络可及点优化方法的研究

容差网络可及点的合理选择,是模拟电路故障诊断理论中一个急待研究的课题,它涉及故障的可诊断性,易觉察性和故障可测度等诸方面问题。本文在文献＾「１,２」的基础上,应用区间分析法探讨容差网络可及点的优化选择。文中提出一系列优化选择可及点的方法和公式,它对工程实际网络的应用都具有一定指导意义。     

接地网故障诊断中的拓扑分解算法

为了对接地网进行故障诊断,通过对接地网支路拓扑结构进行分析,提出了一种以可及节点为裂点的分层拓扑分解方法,将接地网分解为元版块网、可及接地网和本征接地网.实现了接地网网络拓扑自动分解,明确了由拓扑结构决定的各层支路的关联性,为采用可测性进行接地网故障诊断奠定基础.对一个60支路的实验接地网采用所提出的算法进行分解,结果验证了提出的方法的正确性和实用性.     

基于虚拟可及测试节点的模拟电路故障诊断

针对网络撕裂方法诊断模拟电路故障过程中撕裂节点必须是可及节点的限制,提出了虚拟可及测试节点的方法.利用网络拓扑结构和基尔霍夫电流定律计算一类不可及测试节点故障电压,让其成为虚拟可及测试节点.然后在可及或虚拟可及测试节点对网络进行撕裂,再根据故障电压和故障判据定位故障至更小的区域,从而进一步定位故障元件.这种新方法降低了待诊断电路中对可及节点数目的要求,增加了撕裂的灵活性.通过仿真实例验证了该方法的有效性.     

κ故障的ξ可诊性

本文利用摄动理论和流形距离,首次提出了容差电路k故障可诊条件,该条件定量地描述了容差电路可诊性是如何依赖于电路标称数据和可测得信号的。文章还指出了该可诊条件为合理使用定位故障的极值法提供了理论基础。     

κ故障的ξ可诊性

本文利用摄动理论和流形距离,首次提出了容差电路k故障可诊条件,该条件定量地描述了容差电路可诊性是如何依赖于电路标称数据和可测得信号的。文章还指出了该可诊条件为合理使用定位故障的极值法提供了理论基础。     

一种简化的模拟电路测试性评价方法

模拟电路的测试性是进行故障诊断和定位的重要依据.采用基于符号化的分析方法来进行测试性评价,相对于数值计算的方法更有优势.提出了一种测试性矩阵的构建方法,同时给出并证明了基于该测试矩阵进行测试性评价的方法.该评价方法的特点是计算简单实用,且消除了计算误差.最后,通过电路实例,验证了该方法的有效性及其实现上的简洁性.     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

An analytical approach to the partial scan problem

The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.     

Testable Designs of Multiple Precharged Domino Circuits

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults     

Resynthesis of combinational logic circuits for improved path delayfault testability using comparison units

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged     

Testability-based partial scan analysis

In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops in a circuit based on a sensitivity analysis which estimates the relative improvement in the testability of the circuit as a result of scanning a flip-flop. The testability is an estimate of the fault coverage expected for the circuit and is computed with respect to a given set of target faults. Several cost functions are used to compute testability, taking both structural and logical aspects of the circuit into account. Our results show a good correlation between the computed testability and the actual fault coverage. We give a testability-based estimate on the number of scan flip-flops needed to reach a high fault coverage.     

模拟电路的多频灵敏度故障诊断方法

文章在灵敏度故障诊断方法的基础上提出多频灵敏度参数识别故障诊断方法，并给出选择测试频率的一般原则。该方法能够适用于可及测试节点较少的电路。针对模拟电路中一般只存在部分元件故障的情况，进一步提出只识别部分故障元件参数的多频灵敏度故障诊断方法，使该方法能适用于更大规模的电路。电路仿真结果验证了所提方法的有效性。     

Multiple fault analog circuit testing by sensitivity analysis

Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit modeling and testing. The circuit modeling is based on first-order sensitivity computation. The testability of the circuit is analyzed by the multiple-fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing catastrophic and soft faults. Some experimental results are presented for simple models as well as multiple-fault models.     

Multiple fault analog circuit testing by sensitivity analysis

Analog circuit testing is considered to be a very difficult task. This difficulty is mainly due to the lack of fault models and accessibility to internal nodes. To overcome this problem, an approach is presented for analog circuit modeling and testing. The circuit modeling is based on first-order sensitivity computation. The testability of the circuit is analyzed by the multiple-fault model and by functional testing. Component deviations are deduced by measuring a number of output parameters, and through sensitivity analysis and tolerance computation. Using this approach, adequate tests are identified for testing catastrophic and soft faults. Some experimental results are presented for simple models as well as multiple-fault models.     

One method of the circuit diagnosis

In this paper it is shown that properties of orthonormal excitations of the circuit that was used in [1] for deriving sensitivity can as well be used as a mathematical tool for the determination of element values of the analog circuits. Simple methods are then presented for the computation of the circuit elements if all the nodes are accessible.     

基于极零点灵敏度的模拟电路可测性分析

介绍了基于模拟电路极零点灵敏度的分析方法,给出了极零点灵敏度的计算公式。介绍了模拟电路可测性度量的概念,以及基于极零点灵敏度的模拟电路可测性分析方法,给出了求可测性度量的方法。该方法可以用于确定模拟电路的测试点和测试方法。作为例子,对一个3阶电路进行了简要分析。     

基于小波分析和神经网络的模拟电路故障诊断方法

提出了一种基于神经网络和小波分析的模拟电路故障诊断的系统方法。该方法通过对电路的可测性测度计算，选择电路的最佳测试节点，然后利用小波分析作为特征提取手段提取电路的故障特征向量，经归一化和主元分析（PCA）处理后。得到最优特征向量，最后输入到神经网络实现电路故障诊断。计算机仿真结果表明该方法具有更好的故障分辨率。     

High-Level Test Synthesis for Behavioral and Structural Designs

High-Level Test Synthesis (HLTS), a term introduced in recent years, promises automatic enhancement of testability of a circuit. In this paper we will show how HLTS can achieve higher testability for BIST-oriented test methodologies. Our results show considering testability during high-level synthesis, better testability can be obtained when compared to DFT at low level. Transformation for testability, which allows behavioral modification for testability, is a very powerful HLTS technique.     

任意周期激励函数的模拟电路测试激励优化设计

模拟电路测试中不同的激励源会影响电路的可测性,本文根据任意周期函数可由傅立叶级数展开成一个直流分量和一系列正弦函数叠加的原理,设计一种新的基于任意周期激励函数的模拟电路测试激励优化方法.该方法以任意周期激励函数作为优化对象,以最大特征样本的核类间距离作为优化目标,分析待测电路输入输出信号的幅值、频率和相位关系作为约束条...