Effect of collector design on the d.c. characteristics of In0.49Ga0.51P/GaAs heterojunction bipolar transistors

InGaP/GaAs heterojunction bipolar transistors with various collector structures are compared. The dependence of d.c. device characteristics on the thickness of the n⁻ GaAs spacer in the collector of composite collector devices is presented. Results indicate that the spacer thickness significantly affects the performance of the transistor. An n⁺ doping spike on the InGaP side of the collector heterojunction is included in the collector design of the composite collector devices. Standard single-heterojunction d.c. results are compared to abrupt double- and composite collector heterojunction devices. Optimization of the spacer thickness, in conjunction with the n⁺ doping spike, eliminates most of the detrimental effects associated with a double-heterojunction device while retaining the beneficial properties of a wide-gap collector. As expected, the composite collector structure produces devices with higher breakdown voltages and lower offset voltages than single heterojunction devices. In addition, optimizing the spacer thickness can reduce the collector current saturation voltage of the composite collector device below that of a single-heterojunction device. These characteristics make composite collector heterojunction bipolar transistors ideal candidates for high power microwave device applications.     

An Ebers-Moll model for the heterostructure bipolar transistor

An Ebers-Moll model for the heterostructure bipolar transistor (HBT) is developed. The model describes both single and double heterojunction transistors with or without band spikes and applies to uniform or graded base HBTs. Model parameters are directly related to device parameters such as doping densities, dimensions and band spikes. Junction velocities are introduced to describe the transport of carriers across the junctions. Results demonstrate that even for compositionally graded junctions, transport across the junctions may limit HBT performance if the base is graded. Use of the model is illustrated by examining a recently proposed technique for extracting conduction band spikes by comparing forward and inverted I-V characteristics.     

Applications of composite BiCMOS transistors

The concept of the composite CMOS transistor is generalised and extended to include both, composite bipolar and composite BiCMOS transistors. Two versions of the BiCMOS device and its applications in some linear circuits to reduce supply voltage requirements and increase effective transconductance are discussed. Experimental results using transistor arrays are presented.<>     

Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime

The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.      

On crowding effects and failure mechanisms in high power transistor switches

The relationship between current crowding and device failure in the high speed saturating epitaxial transistor switch is discussed. Agreement between theory and practice is demonstrated, using a composite large area device comprising an array of small area transistors.     

Demonstration of npn InAs bipolar transistors with inverted basedoping

We demonstrate np⁺n InAs bipolar transistors that operate under room temperature and cryogenic conditions. InAs transistors on an InP substrate were characterized as a function of temperature and exhibited good room temperature and low temperature common-emitter characteristics. Although the base doping density exceeded the emitter doping density by a factor of 20, current gains of 30 were achieved at room temperature. Junction leakage currents and contact resistance were identified as problems to address     

The Complete Semiconductor Transistor and Its Incomplete Forms

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor,BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

Reliability of AlInAs/GaInAs heterojunction bipolar transistors

The reliability of high-performance AlInAs/GaInAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE) is discussed. Devices with a base Be doping level of 5×10¹⁹ cm^-3 and a base thickness of approximately 50 nm displayed no sign of Be diffusion under applied bias. Excellent stability in DC current gain, device turn-on voltage, and base-emitter junction characteristics was observed. Accelerated life-test experiments were performed under an applied constant collector current density of 7×10⁴ A/cm² at ambient temperatures of 193, 208, and 328°C. Junction temperature and device thermal resistance were determined experimentally. Degradation of the base-collector junction was used as failure criterion to project a mean time to failure in excess of 10⁷ h at 125°C junction temperature with an associated activation energy of 1.92 eV     

Recent developments in power transistors

Power transistors capable of providing five watts output are now in production. Because these units are relatively non-linear in their characteristics, large signal graphical analysis of their behavior is necessary. To facilitate this, the static characteristics of the grounded base, grounded emitter, and grounded collector circuits are presented for several temperatures. Since power transistors are seldom driven with a high impedance source, the input voltages must be known as well as the input currents. These characteristics are drawn to indicate both simultaneously on one chart. The power that must be removed from the junction of these transistors requires that the mounting for the transistor be thermally adequate to remove the heat without allowing the temperature of the Junction to exceed its critical value. The temperature power relationship is discussed and the theoretical size requirements for a heat dissipator are shown for free air convection and forced convection.     

栅条状和蜂窝状结构结势垒肖特基整流器（JBSR）性能对比

栅条状和蜂窝状平面结构的结势垒肖特基整流管（JBSR）的不同之处在于其沟道有效面积的大小不同。从这两种平面结构的结势垒肖特基整流管（JBSR）的工艺和电学特性来看,适当的增大JBSR器件的沟道有效面积,可使JBSR器件的击穿电压得到提高。蜂窝状平面结构JBSR器件的沟道有效面积较栅条状器件的小,开启电压低,但反向耐压不如栅条状平面结构JBSR器件,这可能是因为蜂窝状器件的P+区的缺陷较于栅条状结构器件的多,同样器件的I-V特性也与结构参数密切相关。     

A high-voltage Zener diode with an array structure

A design for a high-voltage Zener diode which employs a technology similar to that used for power MOS transistors is presented. Device performance is improved by patterning the device anode to create an array of small p⁺regions which are connected in parallel to form a composite Zener diode. Results from fabricated devices have verified that the design concept is valid for devices in the voltage range above 400 V, and have provided information on the optimum device geometry.     

Bipolar Microwave Linear Power Transistor Design

Design considerations for n-p-n bipolar microwave linear power transistors are discussed. Optimization procedures are presented for determining emitter width for a specfic operation frequency, emitter ballasting resistance, and active area geometry based on calculated temperature distributions. A transistor chip designed for 4-GHz operations using these procedures achieved a linear power output of 27.5 dBm at a 1-dB compressed gain of 7 dB with a power added efficiency of 23 percent. Junction temperature rise was limited to 90/spl deg/C.     

High-voltage planar devices using field plate and semi-resistivelayers

An improved high-voltage technique based on the use of a field plate combined with semiresistive layers (SIPOS) on oxide is proposed. The field plate and SIPOS (semi-insulating polycrystalline silicon) are shown to have complementary functions. Junction curvature electric field effects are reduced by the presence of the field plate. The silicon surface potential is linearized by a primary SIPOS layer on oxide, thereby reducing the peak electric field at the edge of the field plate. A second high-resistivity SIPOS layer provides an excellent passivation, and also prevents the dielectric breakdown of the underlayer SIPOS film. Moreover, the savings in chip area is about 20% compared to the standard mesa termination. The global yield is 94% for the SIPOS planar transistors and 86% for equivalent devices in mesa technology. The complete fabrication, design, electrical characteristics, and reliability of high-voltage planar transistors are described     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Complementary Josephson junction devices and circuits: a possiblenew approach to superconducting electronics

We present a superconducting logic family whose operation relies on the availability of a current gain greater than one, based on the analogy to semiconductor complementary metal-oxide-semiconductor (CMOS) logic family. The Complementary Josephson Junction (CJJ) logic family utilizes two types of nonlatching devices: a conventional device and a complementary device. The conventional device has a finite critical current, and the complementary device has zero critical current with no input applied. When the input is high, the complementary device has a finite critical current, while the conventional device has zero critical current. The bias current can be steered between a branch with a complementary device and a branch with a conventional device performing logic (and memory) functions. We can also use a resistor as a load to a complementary device. We call this circuit topology the Resistor Complementary Josephson Junction (RCJJ) family. It is analogous to the semiconductor PMOS/resistor logic family. In this paper, we investigate methods of realizing complementary devices, and we present a preliminary analysis of speed, margins, and power dissipation in simple CJJ and RCJJ inverter circuits     

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lays orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mum partially-depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 times 1 bits SRAM column     

The Complete Semiconductor Transistor and Its Incomplete Forms

This paper describes the definition of the complete transistor.For semiconductor devices,the complete transistor is always bipolar,namely,its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions.Partially complete or incomplete transistors,via coined names or/and designed physical geometries,included the 1949 Shockley p/n junction transistor（later called Bipolar Junction Transistor,BJT）,the 1952 Shockley unipolar ＇field-effect＇ transistor（FET,later called the p/n Junction Gate FET or JGFET）,as well as the field-effect transistors introduced by later investigators.Similarities between the surface-channel MOS-gate FET（MOSFET） and the volume-channel BJT are illustrated.The bipolar currents,identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base,led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices,and also the importance of the terminal contacts.     

Printed and Electrochemically Gated,High‐Mobility,Inorganic Oxide Nanoparticle FETs and Their Suitability for High‐Frequency Applications

Solution‐processed or printed n‐channel field‐effect transistors (FETs) with high performance are not reported very often in the literature due to the scarcity of high‐mobility n‐type organic semiconductors. On the other hand, low‐temperature processed n‐channel metal oxide semiconductor (NMOS) transistors from electron conducting inorganic‐oxide nanoparticles show reduced‐performance and low mobility because of large channel roughness at the channel‐dielectric interface. Here, a method to produce ink‐jet printed high performance NMOS transistor devices using inorganic‐oxide nanoparticles as the transistor channel in combination with a 3D electrochemical gating (EG) via printed composite solid polymer electrolytes is presented. The printed FETs produced show a device mobility value in excess of 5 cm² V^?1 s^?1, even though the root mean square (RMS) roughness of the nanoparticulate channel exceeds 15 nm. Extensive studies on the frequency dependent polarizability of composite polymer electrolyte capacitors show that the maximum attainable speed in such printed, long channel transistors is not limited by the ionic conductivity of the electrolytes. Therefore, the approach of combining printable, high‐quality oxide nanoparticles and the composite solid polymer electrolytes, offers the possibility to fully utilize the large mobility of oxide semiconductors to build all‐printed and high‐speed devices. The high polarizability of printable polymer electrolytes brings down the drive voltages to ≤1 V, making such FETs well‐suited for low‐power, battery compatible circuitry.     

GaAs MESFET肖特基结参数表征及其应用

运用双指数函数模型方法分析了影响GaAsMESFET肖特基势垒结特性的各种因素 ,编制了结参数提取和I -V曲线拟合软件 ,实现了通过栅源正向I-V实验数据提取反映肖特基势垒结特性的 6个结参数 ,其结果与实验数据吻合得很好。并对TiAl栅和TiPtAu栅GaAsMESFET进行了高温储存试验前后的结参数对比分析和深能级瞬态谱 (DLTS)验证分析 ,证明这种结参数表征方法是进行器件特性、参数的稳定性与退化和肖特基势垒结质量研究的一种新的实用可行的分析手段。