Temperature‐Dependent Electrical Transport in Polymer‐Sorted Semiconducting Carbon Nanotube Networks

The temperature dependence of the electrical characteristics of field‐effect transistors (FETs) based on polymer‐sorted, large‐diameter semiconducting carbon nanotube networks is investigated. The temperature dependences of both the carrier mobility and the source‐drain current in the range of 78 K to 293 K indicate thermally activated, but non‐Arrhenius, charge transport. The hysteresis in the transfer characteristics of FETs shows a simultaneous reduction with decreasing temperature. The hysteresis appears to stem from screening of charges that are transferred from the carbon nanotubes to traps at the surface of the gate dielectric. The temperature dependence of sheet resistance of the carbon nanotube networks, extracted from FET characteristics at constant carrier concentration, specifies fluctuation‐induced tunneling as the mechanism responsible for charge transport, with an activation energy that is dependent on film thickness. Our study indicates inter‐tube tunneling to be the bottleneck and implicates the role of the polymer coating in influencing charge transport in polymer‐sorted carbon nanotube networks.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.     

Donor–Acceptor Poly(3‐hexylthiophene)‐block‐Pendent Poly(isoindigo) with Dual Roles of Charge Transporting and Storage Layer for High‐Performance Transistor‐Type Memory Applications

Field‐effect transistor memories usually require one additional charge storage layer between the gate contact and organic semiconductor channel. To avoid such complication, new donor–acceptor rod–coil diblock copolymers (P3HT₄₄‐b‐Piso_n) of poly(3‐hexylthiophene) (P3HT)‐block‐poly(pendent isoindigo) (Piso) are designed, which exhibit high performance transistor memory characteristics without additional charge storage layer. The P3HT and Piso blocks are acted as the charge transporting and storage elements, respectively. The prepared P3HT₄₄‐b‐Piso_n can be self‐assembled into fibrillar‐like nanostructures after the thermal annealing process, confirmed by atomic force microscopy and grazing‐incidence X‐ray diffraction. The lowest‐unoccupied molecular orbital levels of the studied polymers are significantly lowered as the block length of Piso increases, leading to a stronger electron affinity as well as charge storage capability. The field‐effect transistors (FETs) fabricated from P3HT₄₄‐b‐Piso_n possess p‐type mobilities up to 4.56 × 10^?2 cm² V^?1 s^?1, similar to that of the regioregular P3HT. More interestingly, the FET memory devices fabricated from P3HT₄₄‐b‐Piso_n exhibit a memory window ranging from 26 to 79 V by manipulating the block length of Piso, and showed stable long‐term data endurance. The results suggest that the FET characteristics and data storage capability can be effectively tuned simultaneously through donor/acceptor ratio and thin film morphology in the block copolymer system.     

Nonvolatile Floating‐Gate Memories Based on Stacked Black Phosphorus–Boron Nitride–MoS2 Heterostructures

Research on van der Waals heterostructures based on stacked 2D atomic crystals is intense due to their prominent properties and potential applications for flexible transparent electronics and optoelectronics. Here, nonvolatile memory devices based on floating‐gate field‐effect transistors that are stacked with 2D materials are reported, where few‐layer black phosphorus acts as channel layer, hexagonal boron nitride as tunnel barrier layer, and MoS₂ as charge trapping layer. Because of the ambipolar behavior of black phosphorus, electrons and holes can be stored in the MoS₂ charge trapping layer. The heterostructures exhibit remarkable erase/program ratio and endurance performance, and can be developed for high‐performance type‐switching memories and reconfigurable inverter logic circuits, indicating that it is promising for application in memory devices completely based on 2D atomic crystals.     

Decoupling the Bias‐Stress‐Induced Charge Trapping in Semiconductors and Gate‐Dielectrics of Organic Transistors Using a Double Stretched‐Exponential Formula

A novel strategy for analyzing bias‐stress effects in organic field‐effect transistors (OFETs) based on a four‐parameter double stretched‐exponential formula is reported. The formula is obtained by modifying a traditional single stretched‐exponential expression comprising two parameters (a characteristic time and a stretched‐exponential factor) that describe the bias‐stress effects. The expression yields two characteristic times and two stretched‐exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer‐side of the interface and the gate‐dielectric layer‐side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate‐dielectric layer were varied systematically. It was found that the gate‐dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias‐stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self‐assembled monolayer further widens the distribution of the activation energy for charge trapping in gate‐dielectric layer‐side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance.     

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100 kHz–2.0 MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.     

Front and Back‐Junction Carbon Nanotube‐Silicon Solar Cells with an Industrial Architecture

In the past, the application of carbon nanotube‐silicon solar cell technology to industry has been limited by the use of a metallic frame to define an active area in the middle of a silicon wafer. Here, industry standard device geometries are fabricated with a front and back‐junction design which allow for the entire wafer to be used as the active area. These are enabled by the use of an intermixed Nafion layer which simultaneously acts as a passivation, antireflective, and physical blocking layer as well as a nanotube dopant. This leads to the formation of a hybrid nanotube/Nafion passivated charge selective contact, and solar cells with active areas of 1–16 cm² are fabricated. Record maximum power conversion efficiencies of 15.2% and 18.9% are reported for front and back‐junction devices for 1 and 3 cm² active areas, respectively. By placing the nanotube film on the rear of the device in a back‐junction architecture, many of the design‐related challenges for carbon nanotube silicon solar cells are addressed and their future applications to industrialized processes are discussed.     

Polarity Effects of Polymer Gate Electrets on Non‐Volatile Organic Field‐Effect Transistor Memory

Organic non‐volatile memory (ONVM) based on pentacene field‐effect transistors (FETs) has been fabricated using various chargeable thin polymer gate dielectrics—termed electrets—onto silicon oxide insulating layers. The overall transfer curve of organic FETs is significantly shifted in both positive and negative directions and the shifts in threshold voltage (V_Th) can be systemically and reversibly controlled via relatively brief application of the appropriate external gate bias. The shifted transfer curve is stable for a relatively long time—more than 10⁵ s. However, this significant reversible shift in V_Th is evident only in OFETs with non‐polar and hydrophobic polymer electret layers. Moreover, the magnitude of the memory window in this device is inversely proportional to the hydrophilicity (determined from the water contact angle) and dielectric polarity (determined from the dielectric constant), respectively. Memory behaviors of ONVM originate from charge storage in polymer gate electret layers. Therefore, the small shifts in V_Th in ONVM with hydrophilic and polar polymers may be due to very rapid dissipation of transferred charges through the conductive channels which form from dipoles, residual moisture, or ions in the polymer electret layers. It is verified that the surface or bulk conductivities of polymer gate electret layers played a critical role in determining the non‐volatile memory properties.     

High‐Performance Top‐Gated Organic Field‐Effect Transistor Memory using Electrets for Monolithic Printed Flexible NAND Flash Memory

High‐performance top‐gated organic field‐effect transistor (OFET) memory devices using electrets and their applications to flexible printed organic NAND flash are reported. The OFETs based on an inkjet‐printed p‐type polymer semiconductor with efficiently chargeable dielectric poly(2‐vinylnaphthalene) (PVN) and high‐k blocking gate dielectric poly(vinylidenefluoride‐trifluoroethylene) (P(VDF‐TrFE)) shows excellent non‐volatile memory characteristics. The superior memory characteristics originate mainly from reversible charge trapping and detrapping in the PVN electret layer efficiently in low‐k/high‐k bilayered dielectrics. A strategy is devised for the successful development of monolithically inkjet‐printed flexible organic NAND flash memory through the proper selection of the polymer electrets (PVN or PS), where PVN/‐ and PS/P(VDF‐TrFE) devices are used as non‐volatile memory cells and ground‐ and bit‐line select transistors, respectively. Electrical simulations reveal that the flexible printed organic NAND flash can be possible to program, read, and erase all memory cells in the memory array repeatedly without affecting the non‐selected memory cells.     

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 10⁴ s and 120 cycles, respectively.     

Understanding the Charge Storage Mechanism to Achieve High Capacity and Fast Ion Storage in Sodium‐Ion Capacitor Anodes by Using Electrospun Nitrogen‐Doped Carbon Fibers

Microporous nitrogen‐rich carbon fibers (HAT‐CNFs) are produced by electrospinning a mixture of hexaazatriphenylene‐hexacarbonitrile (HAT‐CN) and polyvinylpyrrolidone and subsequent thermal condensation. Bonding motives, electronic structure, content of nitrogen heteroatoms, porosity, and degree of carbon stacking can be controlled by the condensation temperature due to the use of the HAT‐CN with predefined nitrogen binding motives. The HAT‐CNFs show remarkable reversible capacities (395 mAh g^?1 at 0.1 A g^?1) and rate capabilities (106 mAh g^?1 at 10 A g^?1) as an anode material for sodium storage, resulting from the abundant heteroatoms, enhanced electrical conductivity, and rapid charge carrier transport in the nanoporous structure of the 1D fibers. HAT‐CNFs also serve as a series of model compounds for the investigation of the contribution of sodium storage by intercalation and reversible binding on nitrogen sites at different rates. There is an increasing contribution of intercalation to the charge storage with increasing condensation temperature which becomes less active at high rates. A hybrid sodium‐ion capacitor full cell combining HAT‐CNF as the anode and salt‐templated porous carbon as the cathode provides remarkable performance in the voltage range of 0.5–4.0 V (95 Wh kg^?1 at 0.19 kW kg^?1 and 18 Wh kg^?1 at 13 kW kg^?1).     

Schottky‐Barrier‐Controllable Graphene Electrode to Boost Rectification in Organic Vertical P–N Junction Photodiodes

Monolayer graphene is used as an electrode to develop novel electronic device architectures that exploit the unique, atomically thin structure of the material with a low density of states at its charge neutrality point. For example, a single semiconductor layer stacked onto graphene can provide a semiconductor–electrode junction with a tunable injection barrier, which is the basis for a primitive transistor architecture known as the Schottky barrier field‐effect transistor. This work demonstrates the next level of complexity in a vertical graphene–semiconductor architecture. Specifically, an organic vertical p‐n junction (p‐type pentacene/n‐type N,N′‐dioctyl‐3,4,9,10‐perylenedicarboximide (PTCDI‐C₈)) on top of a graphene electrode constituting a novel gate‐tunable photodiode device structure is fabricated. The model device confirms that controlling the Schottky barrier height at the pentacene–graphene junction can (i) suppress the dark current density and (ii) enhance the photocurrent of the device, both of which are critical to improve the performance of a photodiode.     

Toward High‐Output Organic Vertical Field Effect Transistors: Key Design Parameters

The performance of C₆₀‐based organic vertical field‐effect transistors (VFETs) is investigated as a function of key geometrical parameters to attain a better understanding of their operation mechanism and eventually to enhance their output current for maximal driving capability. To this end, a 2D device simulation is performed and compared with experimental results. The results reveal that the output current scales mostly with the width of its drain electrode, which is in essence equivalent to the channel width in conventional lateral‐channel transistors, but that of the source electrode and the thickness of C₆₀ layers underneath the source electrode also play subtle but important roles mainly due to the source contact‐limited behavior of the organic VFETs under study. With design strategies acquired from this study, a VFET with an on/off ratio of 5.5 × 10⁵ and on‐current corresponding to a channel length of near 1 μm in a conventional lateral‐channel organic field‐effect transistor (FET) is demonstrated, while the drain width of the VFET and the channel width of the lateral‐channel organic FET are the same.     

Ultrathin MnO2/Graphene Oxide/Carbon Nanotube Interlayer as Efficient Polysulfide‐Trapping Shield for High‐Performance Li–S Batteries

Ultrathin MnO₂/graphene oxide/carbon nanotube (G/M@CNT) interlayers are developed as efficient polysulfide‐trapping shields for high‐performance Li–S batteries. A simple layer‐by‐layer procedure is used to construct a sandwiched vein–membrane interlayer of thickness 2 µm and areal density 0.104 mg cm^?2 by loading MnO₂ nanoparticles and graphene oxide (GO) sheets on superaligned carbon nanotube films. The G/M@CNT interlayer provides a physical shield against both polysulfide shuttling and chemical adsorption of polysulfides by MnO₂ nanoparticles and GO sheets. The synergetic effect of the G/M@CNT interlayer enables the production of Li–S cells with high sulfur loadings (60–80 wt%), a low capacity decay rate (?0.029% per cycle over 2500 cycles at 1 C), high rate performance (747 mA h g^?1 at a charge rate of 10 C), and a low self‐discharge rate with high capacity retention (93.0% after 20 d rest). Electrochemical impedance spectroscopy, cyclic voltammetry, and scanning electron microscopy observations of the Li anodes after cycling confirm the polysulfide‐trapping ability of the G/M@CNT interlayer and show its potential in developing high‐performance Li–S batteries.     

High‐Sensitivity,Skin‐Attachable,and Stretchable Array of Thermo‐Responsive Suspended Gate Field‐Effect Transistors with Thermochromic Display

The fabrication of a skin‐attachable, stretchable array of high‐sensitivity temperature sensors is demonstrated. The temperature sensor consists of a single‐walled carbon nanotube field‐effect transistor with a suspended gate electrode of poly(N‐isopropylacrylamide) (PNIPAM)‐coated gold grid/poly(3,4‐ethylenedioxythiophene) polystyrene sulfonate and thermochromic leuco dye. The sensor exhibits a very high sensitivity of 6.5% °C^?1 at temperatures between 25 and 45 °C. With increasing temperature, the suspended gate electrode bends due to the deswelling of the PNIPAM, resulting in the reduction of the air gap to increase the drain current under a constant gate voltage. At the same time, the leuco dye coated on top of the transparent gate electrode changes color to visualize changes in temperature. The 4 × 6 integrated temperature sensor array integrated using liquid metal interconnections exhibits mechanical and electrical stability under 50% biaxial stretching and allows for the spatial mapping of temperature with visual color display regardless of wrist movement while attached to the skin of the wrist. This work is expected to be widely useful in the development of skin‐attachable electronics for medical and health‐care monitoring.     

The Effect of Gate‐Dielectric Surface Energy on Pentacene Morphology and Organic Field‐Effect Transistor Characteristics

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field‐effect transistors (FETs) are reported, using surface‐energy‐controllable poly(imide‐siloxane)s as gate‐dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three‐dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low‐surface‐energy gate dielectric is larger by a factor of about five, compared to their high‐surface‐energy counterparts. In pentacene growth on the low‐surface‐energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low‐surface‐energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high‐surface‐energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

Integrating Multiple Resistive Memory Devices on a Single Carbon Nanotube

Nano‐objects would be of great interest for the development of new types of electronic circuits if one could combine their nanometer scale with original functionalities beyond the conventional transistor action. However, the associated circuit architectures will have to handle the increasing variability and defect rate intrinsic to the nanoscale. In this context, there is a very fast growing interest for memory devices, and in particular resistive memory devices, used as building blocks in reconfigurable circuits tolerant to defects and variability. It was recently shown that optically gated carbon nanotube field effect transistors (OG‐CNTFETs) based on large assemblies of nanotubes covered by an organic photoconductive thin film can be operated as programmable resistors and thus used as artificial synapses in circuits with function‐learning capabilities. Here, the potential of such approach is evaluated in terms of scalability by integrating and addressing several individually programmable resistances on a single carbon nanotube. In addition, the charge storage mechanism can be controlled at a length scale smaller than the device length allowing to also program the direction in which the current flows. It thus demonstrates that a single nanotube section can combine all‐in‐one the properties of an analog resistive memory and of a rectifying diode with tunable polarity.     

Organic Field‐Effect Transistors and Unipolar Logic Gates on Charged Electrets from Spin‐On Organosilsesquioxane Resins

Controllable shifting of threshold voltage and modulation of current in organic field‐effect transistors (OFETs) is demonstrated, resulting in the formation of unipolar inverters by making use of space‐charge electrets. Prior to the deposition of the organic semiconductor (OSC), negative corona charges are injected and trapped in the bulk of the organosilsesquioxane glass resin gate dielectrics. The effective surface potential is controlled by the corona‐charging and subsequent annealing process. It is found that the shift of the transfer characteristics is governed by the electrostatic induction effects of the charged gate electrets, and this observed shift can be related to the surface potential of the layer next to the transistor channel. The process control, efficiency, and long‐term stability of charge storage in spin‐on organosilsesquioxane glass resins are sufficient to enable the construction of simple unipolar inverters and to allow for circuit tuning. New OFET unipolar inverters with an enhancement‐mode driver and a depletion‐mode load are presented, composed of only two simple OFETs with the same channel dimensions and the same p‐type OSC on charged electrets. This design allows the implementation of full‐swing organic logic circuits and illustrates a potential process simplification for organic electronics.     

Non‐volatile Ferroelectric Poly(vinylidene fluoride‐co‐trifluoroethylene) Memory Based on a Single‐Crystalline Tri‐isopropylsilylethynyl Pentacene Field‐Effect Transistor

A new type of nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) memory based on an organic thin‐film transistor (OTFT) with a single crystal of tri‐isopropylsilylethynyl pentacene (TIPS‐PEN) as the active layer is developed. A bottom‐gate OTFT is fabricated with a thin P(VDF‐TrFE) film gate insulator on which a one‐dimensional ribbon‐type TIPS‐PEN single crystal, grown via a solvent‐exchange method, is positioned between the Au source and drain electrodes. Post‐thermal treatment optimizes the interface between the flat, single‐crystalline ab plane of TIPS‐PEN and the polycrystalline P(VDF‐TrFE) surface with characteristic needle‐like crystalline lamellae. As a consequence, the memory device exhibits a substantially stable source–drain current modulation with an ON/OFF ratio hysteresis greater than 10³, which is superior to a ferroelectric P(VDF‐TrFE) OTFT that has a vacuum‐evaporated pentacene layer. Data retention longer than 5 × 10⁴ s is additionally achieved in ambient conditions by incorporating an interlayer between the gate electrode and P(VDF‐TrFE) thin film. The device is environmentally stable for more than 40 days without additional passivation. The deposition of a seed solution of TIPS‐PEN on the chemically micropatterned surface allows fabrication arrays of TIPS‐PEN single crystals that can be potentially useful for integrated arrays of ferroelectric polymeric TFT memory.