Organic Electronics: High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment (Adv. Funct. Mater. 16/2010)

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Low‐Temperature,Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors

Here, a simple, nontoxic, and inexpensive “water‐inducement” technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water‐induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin‐film transistors (TFTs). The WI indium‐zinc oxide (IZO) TFT integrated on SiO₂ dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm² V^?1 s^?1 and an on‐to‐off current ratio of ≈10⁸. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YO_x dielectric is integrated and investigated. This TFT device can be regarded as “green electronics” in a true sense, because no organic‐related additives are used during the whole device fabrication process. The as‐fabricated IZO/YO_x TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec^?1 and the mobility in excess of 25 cm² V^?1 s^?1.     

Non‐Lithographic Fabrication of All‐2D α‐MoTe2 Dual Gate Transistors

As one of the emerging new transition‐metal dichalcogenides materials, molybdenum ditelluride (α‐MoTe₂) is attracting much attention due to its optical and electrical properties. This study fabricates all‐2D MoTe₂‐based field effect transistors (FETs) on glass, using thin hexagonal boron nitride and thin graphene in consideration of good dielectric/channel interface and source/drain contacts, respectively. Distinguished from previous works, in this study, all 2D FETs with α‐MoTe₂ nanoflakes are dual‐gated for driving higher current. Moreover, for the present 2D dual gate FET fabrications on glass, all thermal annealing and lithography processes are intentionally exempted for fully non‐lithographic method using only van der Waal's forces. The dual‐gate MoTe₂ FET displays quite a high hole and electron mobility over ≈20 cm² V^?1 s^?1 along with ON/OFF ratio of ≈10⁵ in maximum as an ambipolar FET and also demonstrates high drain current of a few tens‐to‐hundred μA at a low operation voltage. It appears promising enough to drive organic light emitting diode pixels and NOR logic functions on glass.     

Self‐Assembled Nanowires of Organic n‐Type Semiconductor for Nonvolatile Transistor Memory Devices

Organic nonvolatile transistor‐type memory (ONVM) devices are developed using self‐assembled nanowires of n‐type semiconductor, N,N′‐bis(2‐phenylethyl)‐perylene‐3,4:9,10‐tetracarboxylic diimide (BPE‐PTCDI). The effects of nanowire dimension and silane surface treatment on the memory characteristics are explored. The diameter of the nanowires is reduced by increasing the non‐solvent methanol composition, which led to the enhanced crystallinity and high field‐effect mobility. The BPE‐PTCDI nanowires with small diameters induce high electrical fields and result in a large memory window (the shifting of the threshold voltage, ΔV_th). The ΔV_th value of BPE‐PTCDI nanowire based ONVM device on the bare substrate can reach 51 V, which is significantly larger than that of thin film. The memory window is further enhanced to 78 V with the on/off ratio of 2.1 × 10⁴ and the long retention time (10⁴ s), using a hydrophobic surface (such as trichloro(phenyl)silane‐treated surface). The above results demonstrate that the n‐type semiconducting nanowires have potential applications in high performance non‐volatile transistor memory devices.     

Tunable Crystal Nanostructures of Pentacene Thin Films on Gate Dielectrics Possessing Surface‐Order Control

To enhance the electrical performance of pentacene‐based field‐effect transistors (FETs) by tuning the surface‐induced ordering of pentacene crystals, we controlled the physical interactions at the semiconductor/gate dielectric (SiO₂) interface by inserting a hydrophobic self‐assembled monolayer (SAM, CH₃‐terminal) of organoalkyl‐silanes with an alkyl chain length of C8, C12, C16, or C18, as a complementary interlayer. We found that, depending on the physical structure of the dielectric surfaces, which was found to depend on the alkyl chain length of the SAM (ordered for C18 and disordered for C8), the pentacene nano‐layers in contact with the SAM could adopt two competing crystalline phases—a “thin‐film phase” and “bulk phase” – which affected the π‐conjugated nanostructures in the ultrathin and subsequently thick films. The field‐effect mobilities of the FET devices varied by more than a factor of 3 depending on the alkyl chain length of the SAM, reaching values as high as 0.6 cm² V^?1 s^?1 for the disordered SAM‐treated SiO₂ gate‐dielectric. This remarkable change in device performance can be explained by the production of well π‐conjugated and large crystal grains in the pentacene nanolayers formed on a disordered SAM surface. The enhanced electrical properties observed for systems with disordered SAMs can be attributed to the surfaces of these SAMs having fewer nucleation sites and a higher lateral diffusion rate of the first seeding pentacene molecules on the dielectric surfaces, due to the disordered and more mobile surface state of the short alkyl SAM.     

Single‐Crystalline p‐Type Zn3As2 Nanowires for Field‐Effect Transistors and Visible‐Light Photodetectors on Rigid and Flexible Substrates

Zn₃As₂ is an important p‐type semiconductor with the merit of high effective mobility. The synthesis of single‐crystalline Zn₃As₂ nanowires (NWs) via a simple chemical vapor deposition method is reported. High‐performance single Zn₃As₂ NW field‐effect transistors (FETs) on rigid SiO₂/Si substrates and visible‐light photodetectors on rigid and flexible substrates are fabricated and studied. As‐fabricated single‐NW FETs exhibit typical p‐type transistor characteristics with the features of high mobility (305.5 cm² V^?1 s^?1) and a high I_on/I_off ratio (10⁵). Single‐NW photodetectors on SiO₂/Si substrate show good sensitivity to visible light. Using the contact printing process, large‐scale ordered Zn₃As₂ NW arrays are successfully assembled on SiO₂/Si substrate to prepare NW thin‐film transistors and photodetectors. The NW‐array photodetectors on rigid SiO₂/Si substrate and flexible PET substrate exhibit enhanced optoelectronic performance compared with the single‐NW devices. The results reveal that the p‐type Zn₃As₂ NWs have important applications in future electronic and optoelectronic devices.     

Transition Metal Dichalcogenide‐Based Transistor Circuits for Gray Scale Organic Light‐Emitting Displays

Two types of transition metal dichalcogenide (TMD) transistors are applied to demonstrate their possibility as switching/driving elements for the pixel of organic light‐emitting diode (OLED) display. Such TMD materials are 6 nm thin WSe₂ and MoS₂ as a p‐type and n‐type channel, respectively, and the pixel is thus composed of external green OLED and nanoscale thin channel field effect transistors (FETs) for switching and driving. The maximum mobility of WSe₂‐FETs either as switch or as driver is ≈30 cm² V^?1 s^?1, in linear regime of the gate voltage sweep range. Digital (ON/OFF‐switching) and gray‐scale analogue operations of OLED pixel are nicely demonstrated. MoS₂ nanosheet FET‐based pixel is also demonstrated, although limited to alternating gray scale operation of OLED. Device stability issue is still remaining for future study but TMD channel FETs are very promising and novel for their applications to OLED pixel because of their high mobility and I _D ON/OFF ratio.     

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS2 Field‐Effect Transistors

2D materials are promising to overcome the scaling limit of Si field‐effect transistors (FETs). However, the insulator/2D channel interface severely degrades the performance of 2D FETs, and the origin of the degradation remains largely unexplored. Here, the full energy spectra of the interface state densities (D_it) are presented for both n‐ and p‐ MoS₂ FETs, based on the comprehensive and systematic studies, i.e., full rage of channel thickness and various gate stack structures with h‐BN as well as high‐k oxides. For n‐MoS₂, D_it around the mid‐gap is drastically reduced to 5 × 10¹¹ cm^?2 eV^?1 for the heterostructure FET with h‐BN from 5 × 10¹² cm^?2 eV^?1 for the high‐k top‐gate. On the other hand, D_it remains high, ≈ 10¹³ cm^?2 eV^?1, even for the heterostructure FET for p‐MoS₂. The systematic study elucidates that the strain induced externally through the substrate surface roughness and high‐k deposition process is the origin for the interface degradation on conduction band side, while sulfur‐vacancy‐induced defect states dominate the interface degradation on valance band side. The present understanding of the interface properties provides the key to further improving the performance of 2D FETs.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

On the Relation between Morphology and FET Mobility of Poly(3‐alkylthiophene)s at the Polymer/SiO2 and Polymer/Air Interface

The influence of the interface of the dielectric SiO₂ on the performance of bottom‐contact, bottom‐gate poly(3‐alkylthiophene) (P3AT) field‐effect transistors (FETs) is investigated. In particular, the operation of transistors where the active polythiophene layer is directly spin‐coated from chlorobenzene (CB) onto the bare SiO₂ dielectric is compared to those where the active layer is first spin‐coated then laminated via a wet transfer process such that the film/air interface of this film contacts the SiO₂ surface. While an apparent alkyl side‐chain length dependent mobility is observed for films directly spin‐coated onto the SiO₂ dielectric (with mobilities of ≈10^?3 cm² V^?1 s^?1 or less) for laminated films mobilities of 0.14 ± 0.03 cm² V^?1 s^?1 independent of alkyl chain length are recorded. Surface‐sensitive near edge X‐ray absorption fine structure (NEXAFS) spectroscopy measurements indicate a strong out‐of‐plane orientation of the polymer backbone at the original air/film interface while much lower average tilt angles of the polymer backbone are observed at the SiO₂/film interface. A comparison with NEXAFS on crystalline P3AT nanofibers, as well as molecular mechanics and electronic structure calculations on ideal P3AT crystals suggest a close to crystalline polymer organization at the P3AT/air interface of films from CB. These results emphasize the negative influence of wrongly oriented polymer on charge carrier mobility and highlight the potential of the polymer/air interface in achieving excellent “out‐of‐plane” orientation and high FET mobilities.     

Layer‐by‐Layer Conjugated Extension of a Semiconducting Polymer for High‐Performance Organic Field‐Effect Transistor

A donor–acceptor (D–A) semiconducting copolymer, PDPP‐TVT‐29, comprising a diketopyrrolopyrrole (DPP) derivative with long, linear, space‐separated alkyl side‐chains and thiophene vinylene thiophene (TVT) for organic field‐effect transistors (OFETs) can form highly π‐conjugated structures with an edge‐on molecular orientation in an as‐spun film. In particular, the layer‐like conjugated film morphologies can be developed via short‐term thermal annealing above 150 °C for 10 min. The strong intermolecular interaction, originating from the fused DPP and D–A interaction, leads to the spontaneous self‐assembly of polymer chains within close proximity (with π‐overlap distance of 3.55 Å) and forms unexpectedly long‐range π‐conjugation, which is favorable for both intra‐ and intermolecular charge transport. Unlike intergranular nanorods in the as‐spun film, well‐conjugated layers in the 200 °C‐annealed film can yield more efficient charge‐transport pathways. The granular morphology of the as‐spun PDPP‐TVT‐29 film produces a field‐effect mobility (μ _FET) of 1.39 cm² V^?1 s^?1 in an OFET based on a polymer‐treated SiO₂ dielectric, while the 27‐Å‐step layered morphology in the 200 °C‐annealed films shows high μ _FET values of up to 3.7 cm² V^?1 s^?1.     

High‐Mobility and Low Turn‐On Voltage n‐Channel OTFTs Based on a Solution‐Processable Derivative of Naphthalene Bisimide

In organic electronics solution‐processable n‐channel field‐effect transistors (FETs) matching the parameters of the best p‐channel FETs are needed. Progress toward the fabrication of such devices is strongly impeded by a limited number of suitable organic semiconductors as well as by the lack of processing techniques that enable strict control of the supramolecular organization in the deposited layer. Here, the use of N,N′‐bis(4‐n‐butylphenyl)‐1,4,5,8‐naphthalenetetracarboxylic‐1,4:5,8‐bisimide (NBI‐4‐n‐BuPh) for fabrication of n‐channel FETs is described. The unidirectionally oriented crystalline layers of NBI‐4‐n‐BuPh are obtained by the zone‐casting method under ambient conditions. Due to the bottom‐contact, top‐gate configuration used, the gate dielectric, Parylene C, also acts as a protective layer. This, together with a sufficiently low LUMO level of NBI‐4‐n‐BuPh allows the fabrication and operation of these novel n‐channel transistors under ambient conditions. The high order of the NBI‐4‐n‐BuPh molecules in the zone‐cast layer and high purity of the gate dielectric yield good performance of the transistors.     

High‐Performance UV–Vis–NIR Phototransistors Based on Single‐Crystalline Organic Semiconductor–Gold Hybrid Nanomaterials

Hybrid materials in optoelectronic devices can generate new functionality or provide synergistic effects that enhance the properties of each component. Here, high‐performance phototransistors with broad spectral responsivity in UV–vis–near‐infrared (NIR) regions, using gold nanorods (Au NRs)‐decorated n‐type organic semiconductor and N ,N ′‐bis(2‐phenylethyl)‐perylene‐3,4:9,10‐tetracarboxylic diimide (BPE‐PTCDI) nanowires (NWs) are reported. By way of the synergistic effect of the excellent photo‐conducting characteristics of single‐crystalline BPE‐PTCDI NW and the light scattering and localized surface plasmon resonances (LSPR) of Au NRs, the hybrid system provides new photo‐detectivity in the NIR spectral region. In the UV–vis region, hybrid nanomaterial‐based phototransistors exhibit significantly enhanced photo‐responsive properties with a photo‐responsivity (R ) of 7.70 × 10⁵ A W^?1 and external quantum efficiency (EQE) of 1.42 × 10⁸% at the minimum light intensity of 2.5 µW cm^?2, which are at least tenfold greater than those of pristine BPE‐PTCDI NW‐based ones and comparable to those of high‐performance inorganic material‐based devices. While a pristine BPE‐PTCDI NW‐based photodetector is insensitive to the NIR spectral region, the hybrid NW‐based phototransistor shows an R of 10.7 A W^?1 and EQE of 1.35 × 10³% under 980 nm wavelength‐NIR illumination. This work demonstrates a viable approach to high‐performance photo‐detecting systems with broad spectral responsivity.     

High‐Mobility Air‐Stable Naphthalene Diimide‐Based Copolymer Containing Extended π‐Conjugation for n‐Channel Organic Field Effect Transistors

A high‐performance naphthalene diimide (NDI)‐based conjugated polymer for use as the active layer of n‐channel organic field‐effect transistors (OFETs) is reported. The solution‐processable n‐channel polymer is systematically designed and synthesized with an alternating structure of long alkyl substituted‐NDI and thienylene–vinylene–thienylene units (PNDI‐TVT). The material has a well‐controlled molecular structure with an extended π‐conjugated backbone, with no increase in the LUMO level, achieving a high mobility and highly ambient stable n‐type OFET. The top‐gate, bottom‐contact device shows remarkably high electron charge‐carrier mobility of up to 1.8 cm² V^?1 s^?1 (I_on/I_off = 10⁶) with the commonly used polymer dielectric, poly(methyl methacrylate) (PMMA). Moreover, PNDI‐TVT OFETs exhibit excellent air and operation stability. Such high device performance is attributed to improved π–π intermolecular interactions owing to the extended π‐conjugation, apart from the improved crystallinity and highly interdigitated lamellar structure caused by the extended π–π backbone and long alkyl groups.     

Bottom‐Up Engineering of Subnanometer Copper Diffusion Barriers Using NH2‐Derived Self‐Assembled Monolayers

A 3‐aminopropyltrimethoxysilane‐derived self‐assembled monolayer (NH₂SAM) is investigated as a barrier against copper diffusion for application in back‐end‐of‐line (BEOL) technology. The essential characteristics studied include thermal stability to BEOL processing, inhibition of copper diffusion, and adhesion to both the underlying SiO₂ dielectric substrate and the Cu over‐layer. Time‐of‐flight secondary ion mass spectrometry and X‐ray spectroscopy (XPS) analysis reveal that the copper over‐layer closes at 1–2‐nm thickness, comparable with the 1.3‐nm closure of state‐of‐the‐art Ta/TaN Cu diffusion barriers. That the NH₂SAM remains intact upon Cu deposition and subsequent annealing is unambiguously revealed by energy‐filtered transmission electron microscopy supported by XPS. The SAM forms a well‐defined carbon‐rich interface with the Cu over‐layer and electron energy loss spectroscopy shows no evidence of Cu penetration into the SAM. Interestingly, the adhesion of the Cu/NH₂SAM/SiO₂ system increases with annealing temperature up to 7.2 J m^?2 at 400 °C, comparable to Ta/TaN (7.5 J m^?2 at room temperature). The corresponding fracture analysis shows that when failure does occur it is located at the Cu/SAM interface. Overall, these results demonstrate that NH₂SAM is a suitable candidate for subnanometer‐scale diffusion barrier application in a selective coating for copper advanced interconnects.     

Enhanced Performance of Self‐Assembled Monolayer Field‐Effect Transistors with Top‐Contact Geometry through Molecular Tailoring,Heated Assembly,and Thermal Annealing

Low‐voltage self‐assembled monolayer field‐effect transistors (SAMFETs) that operate under an applied bias of less than ?3 V and a high hole mobility of 10^?2 cm² V^?1 s^?1 are reported. A self‐assembled monolayer (SAM) with a quaterthiophene semiconducting core and a phosphonic acid binding group is used to fabricate SAMFETs on both high‐voltage (AlO_x/300 nm SiO₂) and low‐voltage (HfO₂) dielectric platforms. High performance is achieved through enhanced SAM packing density via a heated assembly process and through improved electrical contact between SAM semiconductor and metal electrodes. Enhanced electrical contact is obtained by utilizing a functional methylthio head group combined with thermal annealing post gold source/drain electrode deposition to facilitate the interaction between SAM and electrode.     

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 10⁴ s and 120 cycles, respectively.