Current-carrying capacity of anisotropic-conductive film joints for the flip chip on flex applications

The effect of the substrate-pad physical properties (surface roughness and hardness) on the current-carrying capacity of anisotropic-conductive film (ACF) joints is investigated in this work. Flip chips with Au bumps were bonded to the flexible substrates with Au/Cu and Au/Ni/Cu pads using different bonding pressure. It was found that the current-carrying capacity of ACF joints increased to a maximum value with the rise of the bonding pressure; then, it reduced if the bonding pressure continually increased. The maximum average value per unit area of Au/Ni/Cu pad and Au/Cu pad ACF joints is about 93 μA/μm² and 118 μA/μm², respectively, at 100-MPa bonding pressure. The variation trend of connection resistance is the opposite of current-carrying capacity. The variation of current-carrying capacity (or connection resistance) of Au/Cu pad joints is larger than that of Au/Ni/Cu pad joints. The current-carrying capacity is related to the variation of the resistance of ACF joints. The connection resistance of ACF joints depends primarily on the particle constriction resistance (R_coi), R_coi ∞ 1/a, where “a” is the radius of contact spot. A smaller contact area results in larger joule heat generation per unit volume (Q_g), Q_g ∞ 1/a⁴, which preferentially elevates the temperature of the constriction. The raised temperature increases the resistance because of the temperature-dependent coefficient of the metal resistivity. The theory of tribology is used to explain the difference between Au/Cu pad and Au/Ni/Cu pad ACF joints. For the Au/Cu pad ACF joints, the deformation of the particles’ upper and bottom sides is nearly symmetrical; the contact between conductive particles and pad has the character of “sliding contact,” especially under high pressure. For the Au/Ni/Cu pad ACF joint, the contact between particles and pad determined the conduction characteristics of ACF joints. It has the character of “static contact.” Thus, the current-carrying capacity (or connection resistance) of Au/Cu pad joints is more sensitive to the bonding pressure.     

Ultrasonic bonding for multi-chip packaging bonded with non-conductive film

System-on-Chip and System-on-Package technologies have advantages depending on application needs. As a number of electrical and electronic equipment manufacturers have an interest in increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will support next-generation high-end semiconductors such as high speed microprocessors and high speed memories. However, there are many issues regarding process integration, thermal management, and reliability of 3D stacked package.In this study, the printed circuit board (PCB), silicon carrier and silicon chip are integrated with ultrasonic vibration. Die shear tests of the joints were carried out with increasing bonding time and input power to optimize the bonding condition. The integrated chips were successfully bonded to the PCB with and without NCF using a transverse ultrasonic bonding. Electrical resistance of multi-chip bonded with NCF (10 mΩ) measures lower than that bonded without NCF (28.9 mΩ). The voids and delamination were easily found on the joint bonded without NCF that caused lower shear strength.     

Design and fabrication of thin film resistive heaters for hybrid optoelectronic packaging

This paper presents the technology for the design and fabrication of planar resistive heaters made from vacuum deposited nichrome thin films on a quartz substrate. These heaters are suitable as isolated local heat sources for melting solder to attach discrete components on a hybrid optoelectronic integration platform. Numerical simulations are performed using the Finite Element Method (FEM) to determine the geometry of the heaters in order to deliver adequate thermal performance. Multiple heater elements are batch processed on a 3.0 in polished fused quartz wafer using standard photolithographic techniques. Use of polyimide as a reliable insulation layer between the nichrome thin film and the solder has improved the thermal uniformity over the heater surface. Individual heaters can reach temperatures close to 300/spl deg/C drawing 7.1 W of power on an uncooled alumina platform and 12.0 W on an uncooled copper platform. This temperature is high enough to melt gold-tin (AuSn) solder (with eutectic melting point of 280/spl deg/C), typically used for attaching different optoelectronic components on a substrate.     

Epoxy-based aqueous-processable photodielectric dry film andconductive ViaPlug for PCB build-up and IC packaging

DuPont formulated a new generation of photoimageable permanent resists and conductive ViaPlug polymer to be used as building blocks for sequential build-up of printed circuit boards (PCB's), multichip module-laminates (MCM-Ls), and plastic integrated circuit (IC) packages. The buzzwords for these structures are high density interconnection structures (HDIS) and microvias. The conventional method of making PCB's and MCM-Ls is a sequential lamination of innerlayer cores or interplanes, followed by at least one mechanical drilling. In this paper we will discuss a new approach of using semi-additive plating which means starting with a multilayer core, mechanically drilling for through hole connection, filling the through-hole with conductive ViaPlug, then adding layers of dielectric to make blind or buried vias for interconnection and routing of circuits, and heat dissipation. The paper will discuss the challenges in each application, relevant industry specifications for each application, and the dielectric and conductor materials properties to meet the challenges. From the viewpoint of technology choices, we will compare photoimaging versus laser ablation and plasma etching. Lastly, we will discuss our reliability data developed internally and in conjunction with several consortia     

Omnidirectional study of nanostructured glass packaging for solar modules

Antireflective light trapping glass nanostructures fabricated by a non‐lithographic process are investigated for their angle dependent properties to improve the omnidirectional performance of solar modules. Optical transmission and solar cell module I‐V measurements are used to understand the dependence of angular performance of nanostructures in the packaging glass. Nanostructures 100–400 nm in height demonstrate an increase in solar light transmission both for normal as well as oblique incidence and measurements show that a ~200‐400 nm nanostructure height is optimum for solar modules, providing an absolute increase of 1% in the power conversion efficiency at normal incidence and a gain in short circuit current density over a 120° angular cone of solar incidence. This shows that packaging glass texturing can be an important and often‐overlooked method to yield substantial gain in solar module efficiency. Copyright © 2012 John Wiley & Sons, Ltd.     

封装形式对电子元器件长期储存可靠性研究

长期储存是解决军用电子元器件停产断档问题的常用和重要方法之一。本文首先分析了长期储存中电子元器件的失效原因,包括静电、潮湿、温度、污染和震动,然后研究了对封装材料和环境的通用要求以及各封装形式对长期储存的特殊要求,最后比较了每种储存形式的实际寿命和优缺点。证实只要方法得当,每种储存形式均可实现大于15年以上的长期有效储存。     

Comparative study of thermally conductive fillers for use in liquidencapsulants for electronic packaging

Thermal management plays a very vital role in the packaging of high performance electronic devices. Effective heat dissipation is crucial to enhance the performance and reliability of the packaged devices. Liquid encapsulants used for glob top, potting, and underfilling applications can strongly influence the package heat dissipation. Unlike molding compounds, the filler loading in these encapsulants is restrained. This paper deals with the development and characterization of thermally conductive encapsulants with relatively low filler loading. A comparative study on the effect of different ceramic fillers on the thermal conductivity and other critical properties of an epoxy based liquid encapsulant is presented     

一种超薄挠性印制电路用运载膜的研究

文章采用丙烯酸酯压敏胶的粘接原理,调整产品的初粘性和持粘性范围,并采用外交联和内交联相结合固化方式提高产品的耐酸碱和药水的侵蚀能力。并对主要单体、交联单体、固化促进剂、后处理的温度和时间进行了讨论,最终成功开发出了一种可以实际应用的FPC运载膜,为FPC厂家提供了一种成本低,性能好,使用方便的新型辅材。     

A study of moisture diffusion in plastic packaging

The absorption and desorption processes of moisture in plastic material were studied with experimental measurement and finite element (FE) simulation. The diffusion coefficient and the saturate concentration were determined by experiment and simulation results with Fick’s law. The water molecules inside the plastic material were chemically bonded with polymers by hydrogen bonds in the microholes formed by the polymer molecule chains. On the saturate concentration, the moisture density in the effective volumes was 100 times larger than the vapor density in standard state. However, it is only 8% of liquid water. The water inside the plastic material was in a liquid situation. The delamination and the delamination recovery of flip-chip packaging inspected by C-mode scanning acoustic microscropy (C-SAM) during a high-temperature and high-humidity accelerating test could be explained with the state change of the water in plastic material space. The delamination recovery resulted from the increase in content of liquid water. The bonding of water molecules and polymers reduced the adhesive strength at the interface between epoxy material and die, and the delamination on the interface was initiated. A comparison of three cases with noncoated film, top-side SiC_x coated, and both-sides SiC_x coated indicated that the delamination would occur when the moisture concentration was between 50% and 95% of the saturate concentration. During the reflow process, the low interface-adhesive strength and the high vapor pressure of the wet sample might cause popcorning of the plastic packaging. Popcorning could be predicted by simulation of the moisture concentration at the interface.     

先进电子封装中的聚酰亚胺树脂

综述了聚酰亚胺(PI)材料在集成电路制造和先进电子封装中的应用与发展情况。从聚酰亚胺封装材料的基础理论、发展现状、未来发展趋势等几个方面进行了详细的阐述。重点论述了ZKPI系列聚酰亚胺封装材料在芯片表面钝化、层间介电绝缘层膜以及应力缓冲涂层等方面的应用情况。     

Outgassing study of thin films used for poly-SiGe based vacuum packaging of MEMS

Thermal desorption spectroscopy (TDS) was used to study outgassing from polycrystalline SiGe (poly-SiGe), SiC and SiO₂ films used for poly-SiGe-based MEMS thin film vacuum package technology. Primary desorption products were found to be H₂, H₂O and CO₂. The CO₂ outgassing could be correlated with CF₄ plasma interface cleaning used for thick SiGe PECVD, which can leave carbon at the CF₄-plasma-cleaned interface.     

Photolithographic packaging with selectively occupied repeatedtransfer (PL-Pack with SORT) for scalable film optical linkmultichip-module (S-FOLM)

"Photolithographic packaging (PL-pack) with selectively occupied repeated transfer (SORT)" is proposed for optoelectronic microsystem integration. PL-pack with SORT integrates different types of thin-film device pieces into one substrate with desired configurations using an all-photolithographic process. A process design example is presented for a scalable film optical link multichip-module (S-FOLM). A preliminary estimation reveals that PL-Pack with SORT will achieve III-V epitaxial material saving of <1/100 and module cost reduction of <1/10, compared with flip-chip-bonding-based packaging. The result indicates that the process will save on cost and resources simultaneously. A critical issue is how to simplify the procedure for distributing thin-film device pieces onto a substrate. SORT is found to reduce the distribution step count typically by factor of <1/10-1/10000 compared with the conventional one-by-one method. PL-pack with SORT will be extended to the 3R process (reduce, reuse, recycle), which is generally applied to a variety of device/module fabrications     

精简热模型在集成电路封装中的应用研究

探讨了为一款FBGA封装产品建立DELPHI型热阻网络的新方法。首先利用恒温法为芯片封装建立星型网络,在此基础之上求解支路耦合热阻值,构成DELPHI型热阻网络。经过仿真验证显示,所建立的两种DELPHI型热阻网络模型与详细热模型(DTM)的结温误差均在10%以内,从而具备较好的边界条件独立性。     

Micromachined packaging for chemical microsensors

The critical issues involved in chemical microsensor packaging and encapsulation are reviewed and a hybrid solution is presented. In the design approach, the microsensor is divided into two principal physical parts, an electrode and electronics-containing substrate, and a micromachined membrane package. The fabrication and the resultant performance of each part are independently optimizable. The final microsensor is constructed by first binding the two parts together at the wafer level, followed by die separation, and then lead attachment. The micromachined membrane-holders are then filled with liquid membranes to yield functioning sensors. A calcium-ion sensor fabricated by this method is demonstrated     

Reliability of industrial packaging for microsystems

Packaging concepts for silicon-based micromachined sensors exposed to harsh environments are explored. By exposing the sensors directly to the media and applying protection at the wafer level the packaging and assembly will be simplified as compared to conventional methods of fabrication.Protective coatings of amorphous silicon carbide and tantalum oxide are suitable candidates with etch rates below 0.1 Å/h in aqueous solutions with pH 11 at temperatures up to 140°C. Si-Ta-N films exhibit etch rates around 1 Å/h. Parylene C coatings did not etch but peeled off after extended exposure times at elevated temperatures. The best diamond-like carbon films we tested did not etch, but delaminated due to local penetration of the etchants.Several glue types were investigated for chip mounting of the sensors. Hard epoxies, such as Epotek H77, on the one hand exhibit high bond strength and least degradation and leakage, but on the other hand introduce large sensor output drift with temperature changes. Softening of the Epo-tek H77 was observed at 70°C.An industrially attractive thin-film anodic silicon-to-silicon wafer bonding process was developed. Glass layers are deposited at 20 nm/s (1.2 μm/min) by electron-beam evaporation and bond strengths in excess of 25 N/mm² are obtained for bonding temperatures higher than 300°C.Through-hole electrical feedthroughs with a minimum line width of 20μm and a density of 250 wires per cm were obtained by applying electro-depositable photo-resist. Hermetically sealed feedthroughs were obtained using glass frits, which withstand pressures of 4000 bar.     

先进的MEMS封装技术

从特殊的信号界面、立体结构、外壳、钝化和可靠性五个方面总结了MEMS封装的特殊性。介绍了几种当前先进的MEMS封装技术：倒装焊MEMS、多芯片(MCP)和模块式封装(MOMEMS)。最后强调，必须加强MEMS封装的研究。     

Materials for high-density electronic packaging and interconnections in the higher packaging levels

This paper concentrates on the materials requirements anticipated for future packaging strategies of electronic components beyond the 1st level package. This includes Wafer Scale Integration (Level 0), hybrid assembly of bare chips in multichip modules (Level 1.5), printed wiring board (PWB) assembly, including surface mount (Level 2), and higher levels (connectors, mother boards, and cables). Furthermore, high-performance digital VLSI logic packaging only is addressed, to the exclusion of memory, analog, and power circuitry (except power supplies).