Measurement of MOSFET substrate dopant profile via inversionlayer-to-substrate capacitance

In this paper, a new method for extracting substrate dopant concentration profile of short-channel MOSFET's is presented. It is based on the measurement of the small-signal capacitance between the inversion layer and the substrate. The method achieves effective deep depletion through dc reverse bias on the inversion-to substrate junction and thus avoids the problems with transients associated with pulsed C-V of MOS capacitors. By using transistors of different drawn lengths the effect of lateral extension of drain and source junction depletion regions is also accounted for     

Inversion charge modeling

A simple, implicit, relation for the inversion charge density in the channel of metal oxide semiconductor (MOS) transistors is presented. The relation is continuous and covers the whole operating range, from subthreshold to strong inversion. The derivative of the local inversion charge density with respect to the channel voltage is a simple expression in the charge density, leading to analytic integrals as required for obtaining the drain current and the capacitance coefficients     

一种新的MOS结构量子化效应修正模型

从载流子在 MOS结构反型层内的经典分布和量子化后的子带结构出发 ,提出了经典的和量子化的表面有效态密度 (SL EDOS:Surface layer effective density- of- states)的概念。利用表面有效态密度的概念建立了经典理论框架和量子力学框架内的电荷分布模型。该模型包含了强反型区表面电势的变化对载流子浓度的影响 ,具有很高的计算效率和稳定性。在模型基础上 ,研究了量子化效应对反型层载流子浓度和表面电势的影响。     

C-VCharacterization in MOS Structure Inversion Layer Including Quantum Mechanical Effects

A simplified method to calculate the band bending and subband energy is presented to investigate the Quantum Mechanical Effects (QMEs) in MOS structure inversion layer. The method is fairly unique compared with the published methods in the reversed nature of the iteration procedure. It has high efficiency and good convergence characteristics. Gate capacitance in MOS structure inversion region is formulated in both quantum mechanical cases and semi-classical cases and Quantum Mechanical Effects on gate capacitance have been analyzed. Results of different substrate doping levels are compared and the substrate doping concentration dependence of QMEs on gate capacitance is studied. It is shown that QMEs lead to a substantial decrease in gate capacitance in the strong inversion region. Results of different substrate doping levels indicate that the QMEs on gate capacitance are different substantially in the threshold region at different substrate doping levels but almost the same in the strong inversion region.     

C-VCharacterization in MOS Structure Inversion Layer Including Quantum Mechanical Effects

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基于有效态密度的MOS结构电荷控制模型

从载流子在 MOS结构反型层内的分布出发 ,利用表面有效态密度 ( SLEDOS:SurfaceLayer Effective Density- of- States)的概念 ,在经典理论框架内建立了包含载流子分布对表面势影响的电荷控制模型 .该模型包含了强反型区表面电势的变化对载流子浓度的影响 ,采用了一种新的高效的迭代方法 ,具有较高的计算效率和足够的精度要求     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of theG/omegaversus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.     

Quantum effects in Si n-MOS inversion layer at high substrate concentration

The charge distribution at the semiconductgor-insulator interface is calculated for electrons by solving Schrödinger's and Poisson's equations self-consistently for particles obeying Fermi-Dirac statistics at 300 K. The results are applied to carriers in the channel of a crystalline MOSFET with the (100) axis perpendicular to the gate oxide. The inversion charge density calculated quantum mechanically is smaller than that calculated classically. This affects the shift of the subthreshold curves. The shift is larger at higher substrate impurity concentrations, and is especially pronounced at more than 10¹⁷ cm⁻³, which is the concentration used in recent MOS devices. The shift is as large as 0.18 V when the substrate impurity concentration is 8.5 × 10¹⁷ cm⁻³. Comparisons with measurement are also shown and it agrees well with quantum mechanical calculations. The inversion layer depth is compared, and a new efficient method is derived by transferring the quantum mechanical effect into the classical calculation. The results of this new method agree well with the quantum mechanical calculations and with the measurements.     

An improved electron and hole mobility model for general purposedevice simulation

A new, comprehensive, physically-based, semiempirical, local model for transverse-field dependent electron and hole mobility in MOS transistors is presented. In order to accurately predict the measured relationship between the effective mobility and effective electric field over a wide range of substrate doping and bias, we account for the dependence of surface roughness limited mobility on the inversion charge density, in addition to including the effect of coulomb screening of impurities by charge carriers in the bulk mobility term. The result is a single mobility model applicable throughout a generalized device structure that gives good agreement with measured mobility data and measured MOS I-V characteristics over a wide range of substrate doping, channel length, transverse electric field, substrate bias, and temperature     

Body bias dependence of 1/f noise in NMOS transistors fromdeep-subthreshold to strong inversion

Dependence of 1/f noise on the body-to-source junction bias voltages (V_BS) between -2.5 and 0.5 V for 0.25-μm NMOS transistors is reported. In subthreshold, 1/f noise is reduced by about one order of magnitude, when the body-to-source junction is forward biased by 0.5 V (V_BS) compared to that for V_BS=0 V, which is due to increased depletion layer capacitance as well as possibly due to an increased average distance between oxide traps and carriers caused by the forward bias. On the contrary, in strong inversion, 1/f noise remains almost constant for the entire V_BS range     

Inversion charge redistribution model of the high-frequency MOS capacitance

The high-frequency semiconductor capacitance in an MOS structure is ordinarily calculated by a depletion-charge analysis approach assuming that there is no response of the inversion layer charge to the a.c. signal. The more realistic model, in which the inversion charge is allowed to be spatially redistributed at the high frequency, is treated here by the solution of the Poisson-Boltzmann equation incorporating an appropriate quasi-Fermi level for the inversion layer carriers. The inclusion of this effect leads to a much faster saturation of the capacitance and increases the value at strong inversion by 2–5 per cent for silicon at room temperature. It also predicts a shallow minimum less than 1 per cent below the asymptotic value. Agreement with experiment is shown to be excellent. An analytic expression for the asymptotic value is given.     

Analytical model for high-performance shallow-junction-welltransistor (SJET) with a fully depleted channel structure

An analytical model for a very-shallow-junction-well transistor (SJET) is described. Solving the one-dimensional Poisson equation at the channel region, it was found that the channel depletion-layer charge can be reduced by extending the p-n junction depletion layer width between the well region and the substrate in the SJET. Therefore, in the SJET, the p-well thickness and the substrate bias are very important factors for realizing its high performance. According to this model, larger carrier mobility in the inversion layer and smaller subthreshold swing can be realized in the SJET compared to a conventional MOSFET. Moreover, by controlling the electron injection from the inversion layer to the substrate at high substrate bias, a vertical operating mode in the SJET (VSJET) can also be realized     

The effect of small-signal AC voltages on C–V characterization and parameter extraction of SiO2 thin films

The effect of different small-signal ac voltage amplitudes on C–V curves characterized by thin SiO₂ based p-type MOS capacitor with aluminum gate is reported. When the small-signal ac voltage is comparable to the gate bias, the thickness of SiO₂ thin films extracted from the accumulation capacitance is found to be independent of small-signal ac voltage amplitudes, but the flat band voltage shift and interface state density associated with the variation of depletion layer capacitance are dependent on small-signal ac voltage amplitudes. They all increase with the small-signal ac voltage amplitudes. The experimental results reveal that the optimum small-signal ac voltage should be less than 100 mV. The mechanisms involving the depletion layer changes with small-signal ac voltages in SiO₂ thin films are also discussed in this paper.     

An improved formula for the determination of the polysilicon doping

This letter describes an improved formula for the extraction of the polysilicon doping from the C-V characteristic of MOS transistors. Analytical approximations are presented for the inversion layer contribution, which was neglected in previous work. The new approach returns an estimate error smaller than 10% when the full substrate and poly quantization are accounted for. Practical application to experimental data is also addressed     

Effects of measurement frequency and temperature anneal on differential gate capacitance spectra observed in hot carrier stressed MOSFET's

Hot carrier generated fixed and interface traps, located at the Si-SiO/sub 2/ interface near the drain junction, are observed from the gate-to-drain capacitance of the MOS transistor, using an AC measurement signal applied to the drain. When the channel is biased in inversion, the drain junction is forward biased and carriers from the AC signal source are readily injected into the channel, leading to charge exchange between the inversion carriers and the traps located in one half of the band gap. In channel depletion, the drain junction is reverse biased, and charge exchange is between the substrate majority carriers and traps located in the other half of the band gap. The charge interaction manifests itself in a differential gate capacitance, extracted from pre- and post-stress gate capacitance voltage curves. The differential capacitance spectrum shows two distinct peaks, which are attributed to the response of donor and acceptor interface traps, located on either half of the band gap. This model is supported by capacitance measurements at different frequencies. Lower frequencies lead to a proportionally larger increase in the depletion regime response. Prolonged stress results in the convolution of the two peaks. A reverse bias on the drain leads to the deconvolution of the spectrum, allowing the two peaks to be clearly resolved. Trap response may be masked by the fixed charge, but this can be overcome by depopulation of trapped electrons or neutralization of trapped holes through elevated temperature anneal. The differential gate-to-drain capacitance allows the electrical identification of both donor and acceptor interface traps in the same device.<>     

High frequency space charge layer capacitance of strongly inverted semiconductor surfaces

The finite spatial extension of the inversion layer minority carriers shunts the dielectric capacitance of the inversion layer and increases the high frequency semiconductor surface space charge layer capacitance in the strong inversion range by about 5 per cent. This distributed minority carrier distribution also gives rise to a small (about 1 per cent) high frequency capacitance minimum near the onset of strong surface inversion. A simple two-lump model is developed which is accurate to within 0·4 per cent of the numerical solution obtained from the exact transmission line model. Applied gate voltages at the capacitance minimum are presented graphically as a function of oxide thickness with the substrate impurity concentration as a parameter. Surface quantization effect is not taken into account.     

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

Interface trap densities at gate oxide/silicon substrate (SiO₂/Si) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.     

On the accuracy of the theoretical high-frequency semiconductor capacitance for inverted MOS structures

The accuracy of the usual expression of the high-frequency semiconductor capacitance is investigated by means of a charge-analysis model which takes into account the minority carrier rearrangement within the inversion layer due to the ac signal. In the range of doping concentrations of practical interest, it is found that the errors never exceed 5 percent, even in the strong inversion region.     

Enhanced capacitor for one-transistor memory cell

Ion implantation has been used to increase the depletion-layer capacitance beneath the inversion layer of an MOS capacitor in order to enhance the charge storage per unit area. Boron and arsenic implants were used to increase the depletion-layer capacitance, approximately halving the area required for a given charge storage.