Modeling selective attention using a neuromorphic analog VLSI device

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.     

Dynamic wires: An alanog VLSI model for object-based processing

The dynamic-wire methodology provides dedicated lines of communication among groups of pixels of an image which share common properties. In simple applications, object regions can be grouped together to compute the area or the center of mass of each object. Alternatively, object boundaries may be used to compute curvature or contour length. These measurements are useful for higher-level tasks such as object recognition or structural saliency. The dynamic-wire methodology is efficiently implemented in fast, low-power analog hardware. Switches create a true electrical connection among selected pixels, dynamically configuring wires or resistive networks on the fly. Dynamic wires provide a model for object-based processing. This approach is different from present early vision chips which are limited to pixel-based or image-based operations. Using this methodology, we have successfully designed and demonstrated a custom analog VLSI chip which computes contour length.     

A CMOS binary pattern classifier based on Parzen''s method

Biological circuitry in the brain that has been associated with the Parzen method of classification inspired an analog CMOS binary pattern classifier. The circuitry resides on three separate chips. The first chip computes the closeness of a test vector to each training vector stored on the chip where "vector closeness" is defined as the number of bits two vectors have in common above some thresholds. The second chip computes the closeness of the test vector to each possible category where "category closeness" is defined as the sum of the closenesses of the test vector to each training vector in a particular category. Category closenesses are coded by currents which feed into an "early bird" winner-take-all circuit on the third chip that selects the category closest to the test vector. Parzen classifiers offer superior classification accuracy than the common nearest neighbor Hamming networks. A high degree of parallelism allows for O(1) time complexity and the chips are tillable for increased training vector storage capacity. Proof-of-concept chips were fabricated through the MOSIS chip prototyping service and successfully tested.     

Silicon auditory processors as computer peripherals

Several research groups are implementing analog integrated circuit models of biological auditory processing. The outputs of these circuit models have taken several forms, including video format for monitor display, simple scanned output for oscilloscope display, and parallel analog outputs suitable for data-acquisition systems. Here, an alternative output method for silicon auditory models, suitable for direct interface to digital computers, is described. As a prototype of this method, an integrated circuit model of temporal adaptation in the auditory nerve that functions as a peripheral to a workstation running Unix is described. Data from a working hybrid system that includes the auditory model, a digital interface, and asynchronous software are given. This system produces a real-time X-window display of the response of the auditory nerve model.     

A neuromorphic VLSI device for implementing 2D selective attentionsystems

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.     

Voiced-speech representation by an analog silicon model of theauditory periphery

An analog CMOS integration of a model for the auditory periphery is presented. The model consists of middle ear, basilar membrane, and hair cell/synapse modules which are derived from neurophysiological studies. The circuit realization of each module is discussed, and experimental data of each module's response to sinusoidal excitation are given. The nonlinear speech processing capabilities of the system are demonstrated using the voiced syllable |ba|. The multichannel output of the silicon model corresponds to the time-varying instantaneous firing rates of auditory nerve fibers that have different characteristic frequencies. These outputs are similar to the physiologically obtained responses. The actual implementation uses subthreshold CMOS technology and analog continuous-time circuits, resulting in a real-time, micropower device with potential applications as a preprocessor of auditory stimuli.     

An adaptive neural processing node

The design and test results for two analog adaptive VLSI processing chips are described. These chips use pulse coded signals for communication between processing nodes and analog weights for information storage. The weight modification rule, implemented on chip, uses concepts developed by E. Oja (1982) and later extended by T. Leen et al. (1989) and T. Sanger (1989). Experimental results demonstrate that the network produces linearly separable outputs that correspond to dominant features of the inputs. Such representations allow for efficient additional neural processing. Part of the adaptation rule also includes a small number of fixed inputs and a variable lateral inhibition mechanism. Experimental results from the first chip show the operation of function blocks that make a single processing node. These function blocks include forward transfer function, weight modification, and inhibition. Experimental results from the second chip show the ability of an array of processing elements to extract important features from the input data.     

Discrimination of speech from nonspeech based on multiscale spectro-temporal Modulations

We describe a content-based audio classification algorithm based on novel multiscale spectro-temporal modulation features inspired by a model of auditory cortical processing. The task explored is to discriminate speech from nonspeech consisting of animal vocalizations, music, and environmental sounds. Although this is a relatively easy task for humans, it is still difficult to automate well, especially in noisy and reverberant environments. The auditory model captures basic processes occurring from the early cochlear stages to the central cortical areas. The model generates a multidimensional spectro-temporal representation of the sound, which is then analyzed by a multilinear dimensionality reduction technique and classified by a support vector machine (SVM). Generalization of the system to signals in high level of additive noise and reverberation is evaluated and compared to two existing approaches (Scheirer and Slaney, 2002 and Kingsbury et al., 2002). The results demonstrate the advantages of the auditory model over the other two systems, especially at low signal-to-noise ratios (SNRs) and high reverberation.     

Transcending Turing Computability

It has been argued that neural networks and other forms of analog computation may transcend the limits of Turing-machine computation; proofs have been offered on both sides, subject to differing assumptions. In this article I argue that the important comparisons between the two models of computation are not so much mathematical as epistemological. The Turing-machine model makes assumptions about information representation and processing that are badly matched to the realities of natural computation (information representation and processing in or inspired by natural systems). This points to the need for new models of computation addressing issues orthogonal to those that have occupied the traditional theory of computation.     

新的保持边缘的图像放大算法

为了适应视频后处理芯片低成本的需求,提出一种仅需用两行缓存的新的保持边缘的图像放大算法。该方法寻找代表点代替插值点来确定相关方向。找到相关方向后,对应方向上寻找四个邻域点及其对应位置,进行插值。实验结果表明该算法能实现图像的放大,并能消除图像边缘模糊和锯齿效应,可应用于低成本的数字视频后处理芯片中。     

Computing motion using analog VLSI vision chips: An experimental comparison among different approaches

We have designed, built and tested a number of analog CMOS VLSI circuits for computing 1-D motion from the time-varying intensity values provided by an array of on-chip phototransistors. We present experimental data for two such circuits and discuss their relative performance. One circuit approximates the correlation model while a second chip uses resistive grids to compute zero-crossings to be tracked over time by a separate digital processor. Both circuits integrate image acquisition with image processing functions and compute velocity in real time. For comparison, we also describe the performance of a simple motion algorithm using off-the-shelf digital components. We conclude that analog circuits implementing various correlation-like motion algorithms are more robust than our previous analog circuits implementing gradient-like motion algorithms.     

基于音频编解码器TLV320AIC23与FPGA/CPLD的数字化语音处理系统

提供了基于FPGA/CPLD的数字化音频处理系统的典型解决方案。该方案由语音芯片(TLV320AIC23)和处理器(FPGA/CPLD)两部分组成。语音芯片完成模拟语音信号与数字信号之间的相互转换,包括ADC和DAC;处理器则完成对经模数转换后的语音信号在数字域处理的过程。该方案可以充分发挥FPGA/CPLD所具有的灵活性好、实时性能高及并行处理能力强的特点。     

基于ZigBee无线传感网络技术节点设计与实现

利用各类传感器采集外界信息,产生模拟电压信号,通过模数转换进而得到数字信号,摒弃传统的有线串口发数模式,用CC2430芯片作为节点的核心芯片,负责数据处理和无线射频工作。根据以上要求给出了系统硬件结构及软件设计方案,并综合考虑到了节点的功耗问题。     

Systems technologies for silicon auditory models

Presents a low-power analog integrated circuit which implements a biologically inspired algorithm for the spectral analysis of sound. The chip features an efficient interface to digital systems; preserving analog processing's low-power, high-density advantages requires careful attention to interface issues. To send the spectral representation off chip, it generates a sparse coding of the output spectrum, and communicates the code as an asynchronous stream of events. We store parameters for the spectral analysis algorithm as charge on floating nodes, and support the modification of these parameters via Fowler-Nordheim tunneling, under the control of a digital interface. A prototype system uses this chip as a preprocessor     

Constraint-based sensor planning for scene modeling

We describe an automated scene modeling system that consists of two components operating in an interleaved fashion: an incremental modeler that builds solid models from range imagery; and a sensor planner that analyzes the resulting model and computes the next sensor position. This planning component is target-driven and computes sensor positions using model information about the imaged surfaces and the unexplored space in a scene. The method is shape-independent and uses a continuous-space representation that preserves the accuracy of sensed data. It is able to completely acquire a scene by repeatedly planning sensor positions, utilizing a partial model to determine volumes of visibility for contiguous areas of unexplored scene. These visibility volumes are combined with sensor placement constraints to compute sets of occlusion-free sensor positions that are guaranteed to improve the quality of the model. We show results for the acquisition of a scene that includes multiple, distinct objects with high occlusion     

Development of an ASIC set for signal processing

An approach to signal acquisition, digitization, and processing of low-frequency physiological signals is discussed. The approach uses a chip attached to a transducer through a digital wire placed at the sensing point. The wire transmits digital information instead of an analog signal to an application-specific integrated circuit (ASIC) signal processor. This digital wire/Visp chip set produces a noise-immune signal processing system usable in a variety of biosignal processing needs. The concept is demonstrated using the Visually Evoked Potential (VEP) measurement system     

A sensorimotor approach to sound localization

Sound localization is known to be a complex phenomenon, combining multisensory information processing, experience-dependent plasticity, and movement. Here we present a sensorimotor model that addresses the question of how an organism could learn to localize sound sources without any a priori neural representation of its head-related transfer function or prior experience with auditory spatial information. We demonstrate quantitatively that the experience of the sensory consequences of its voluntary motor actions allows an organism to learn the spatial location of any sound source. Using examples from humans and echolocating bats, our model shows that a naive organism can learn the auditory space based solely on acoustic inputs and their relation to motor states.     

An analog silicon retina with multichip configuration

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study . The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.     

飞行控制计算机采集处理系统的设计与实现

针对飞行控制计算机对无人机姿态和航迹信息采集处理的要求,本文给出以DSP TMS320LF2407A为平台的模拟量、通讯量、开关量采集处理的设计方案。该方案分别阐述了模拟量、通讯量、开关量接口电路、片选控制逻辑和类8259中断控制逻辑的CPLD思想、硬件滤波和软件抗干扰思想。该采集处理系统硬件接口简洁、实时性强、抗干扰特性好,具有很强的工程应用性。     

Application of the ANNA neural network chip to high-speed characterrecognition

A neural network with 136000 connections for recognition of handwritten digits has been implemented using a mixed analog/digital neural network chip. The neural network chip is capable of processing 1000 characters/s. The recognition system has essentially the same rate (5%) as a simulation of the network with 32-b floating-point precision.