Self-aligned ion implant masking for CMOS VLSI technology

Conventional self-aligned ion implantation masking is often inadequate in CMOS VLSI fabrication. We describe a method of increasing this ion implant masking with minimal additional processing. Scanning electron micrographs portray the enhanced ion implant masking.     

High-density and reduced latchup susceptibility CMOS technology for VLSI

Increasing layout density and reducing susceptibility to latchup are two of the most pressing concerns in making CMOS a superior VLSI technology. This work presents a possible solution to these CMOS issues. Significant reductions of the well (in our case p-well) resistance and of the well side diffusion are the results of the incorporation of a heavily doped epitaxial buried layer in the CMOS process. Using this approach n⁺-p⁺spacings of 3.5 µm give adequate punchthrough margin for 5-V operation and, compared to a conventional CMOS process, a sevenfold improvement in holding current.     

Design of a DPCM codec for VLSI realization in CMOS technology

Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.     

Selective epitaxy for CMOS VLSI

Scaling CMOS for VLSI is difficult owing to increasing latchup susceptibility and lateral diffusion of the well which limits packing density. A novel solution to these problems is presented, using selective epitaxial deposition to refill etched wells. In conjunction with a buried-layer implant, a retrograde well profile is achieved with a low sheet resistivity (440 Ω), giving reduced latchup susceptibility. Shallow wells can be used (typically 1 µm) with source/drain-to-well breakdown voltages greater than 9.5 V. Transistor characteristics are good with a long-channel mobility of 192 cm²/V.s and subthreshold slope of 100-mV/decade for a 2.5-µm channel length.     

A novel CMOS VLSI isolation technology using selective chlorineimplantation

An isolation technology that uses blanket boron and selective chlorine n-well implantation prior to field oxidation is proposed. Chlorine implantation results in an increase in the thermal-oxidation linear-reaction-rate coefficient by a factor of 11.5, which enhances the segregation of dopant atoms in the n-well field region. Due to the redistribution of dopant atoms in the n-well field region, the field threshold voltage magnitude may be increased by as much as 20 V when chlorine implantation is used     

Iddq testing for CMOS VLSI

It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq testing as an integral part of the overall testing for all IC's. This paper describes the present status of Iddq testing along with the essential items and necessary data related to Iddq testing. As part of the introduction, a historical background and discussion is given on why this test method has drawn attention. A section on physical defects with in-depth discussion and examples is used to illustrate why a test method outside the voltage environment is required. Data with additional information from case studies is used to explain the effectiveness of Iddq testing. In Section IV, design issues, design styles, Iddq test vector generation and simulation methods are discussed. The concern of whether Iddq testing will remain useful in deep submicron technologies is addressed (Section V). The use of Iddq testing for reliability screening is described (Section VI). The current measurement methods for Iddq testing are given (Section VII) followed by comments on the economics of Iddq testing (Section VIII). In Section IX pointers to some recent research are given and finally, concluding remarks are given in Section X     

CMOS on buried nitride—A VLSI SOI technology

A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.     

Characterization of CMOS Devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Olpthnum performance (minimum figure of merit FM= f/sub pd/P/sub d/) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, C/sub L/ = 22 fF) with an electrical channel length L = 0.75 /spl mu/m, channel width W= 5.0 /spl mu/m, and oxide thickness X/sub O/ = 450 /spl Aring/with V/sub DD/ = 3.0 V, to yield t/sub pd/ = 400 ps and P/sub d/ = 250 /spl mu/W (t/sub pd/P/sub d/ = 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for t/sub pd/ and P/sub d/. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for t/sub pd/ describes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchal modeling approach to characterize mini-cells for VLSI.     

A Design Style for VLSI CMOS

CMOS is an attractive technology for the realization of VLSI systems. However conventional static CMOS design techniques lead to circuits which are slower and much less densely packed than equivalent NMOS circuits. After a brief review of precharge-discharge techniques, a novel method for designing clocked dynamic CMOS is described. This uses a four-phsse clocking scheme that is free from race and charge-sharing problems and results in faster, more compact layouts. A test chip and a full custom 25 000 transistor serial signal processing chip have been designed using this technique. Results obtained by probing the test ship are presented.     

Characterization of CMOS devices for VLSI

CMOS bulk and SOS technologies are discussed for VLSI with emphasis on static and dynamic characteristics of two-input NAND gates. Optimum performance (minimum figure of merit FM = tpdPd) is obtained for a CMOS/SOS two-input NAND gate (FO = 2, CL= 22 fF) with an electrical channel length L = 0.75 µm, channel width W = 5.0 µm, and oxide thickness Xo= 450 Å with VDD= 3.0 V, to yield tpd= 400 ps and Pd= 250 µW (tpdPd= 100 fJ) at room temperature. Bulk technology performs within a factor of 2 of SOS for tpdand Pd. CMOS technologies offer subnanosecond propagation delays, similar to ECL bipolar, at the low submilliwatt power levels of CMOS. An analytical expression for tpddescribes the performance of two-input NAND gates in terms of device modeling and fabrication parameters. Such an expression provides a hierarchial modeling approach to characterize minicells for VLSI.     

CMOS VLSI设计技术

本文从电路组态,逻辑组态、匹配技术和设计方法上讨论了CMOS VLSI设计技术,以及如何实现高速低功耗和高门密度设计.     

Switched-capacitor broadband noise generator for CMOS VLSI

A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the implementation of a very simple chaotic discrete-time system. The concept is demonstrated via a 3 mu m CMOS double-metal double-poly monolithic prototype yielding a 4 V peak-to-peak signal with a flat power density spectrum from DC to about half the clock frequency.<>     

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are ± 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 µAV^-2. The bipolar transistors have a low-resistance base contact. Current gain βFcan be set independently. Forbeta_{F} = 90, the Early voltage isV_{A} = 110V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.     

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

MOS technology for VLSI

The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.     

CMOS VLSI ESD保护电路设计技术

本文对CMOSVLSI芯片ESD失效现象及其ESD事件发生机理进行了分析,介绍了CMOSVLSIESD保护电路设计技术。使用具有大电流放电性能的MOS器件构成的ESD电路,以及采用周密的版图布局布线技术,可实现良好的ESD保护性能。     

Punchthrough current for submicrometer MOSFETs in CMOS VLSI

Simulated and measured data show that drain-induced barrier lowering (DIBL) in buried-channel MOSFETs is different from that in surface channel (SC) MOSFETs. This is explained by the differences between channel current paths and channel potential distribution. A new parameter, defined as the incremental voltage that the drain can sustain before the punchthrough current increases by an order of magnitude, is used to indicate the rate of increase of punchthrough current and is a measure of DIBL