基于SoC设计的软硬件协同验证方法学

文章介绍了软硬件协同验证方法学及其验证流程。在软件方面，采用了一套完整的软件编译调试仿真工具链，它包括处理器的仿真虚拟原型和基本的汇编、链接、调试器；在硬件方面，对软件调试好的应用程序进行RTL仿真、综合，并最终在SoC设计的硬件映像加速器（FPGA）上实现并验证。     

An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming

One of the key problems in hardware/software codesign is hardware/software partitioning. This paper describes a new approach to hardware/software partitioning using integer programming (IP). The advantage of using IP is that optimal results are calculated for a chosen objective function. The partitioning approach works fully automatic and supports multi-processor systems, interfacing and hardware sharing. In contrast to other approaches where special estimators are used, we use compilation and synthesis tools for cost estimation. The increased time for calculating values for the cost metrics is compensated by an improved quality of the values. Therefore, fewer iteration steps for partitioning are needed. The paper presents an algorithm using integer programming for solving the hardware/software partitioning problem leading to promising results.     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

Rapid Prototyping of Embedded Hardware/Software Systems

Prototyping of embedded hardware/software systems is important, because it shortens the path from specification to the final product. Prototypes play a major role in decision making, concept and design validation, feature and limit exploration, as well as design verification in every phase of the product development cycle, including product planning, requirement engineering, and product development. This overview discusses the motivation for building prototypes, provides the key areas for research and explains how prototypes can assist in product planning and throughout all steps of the engineering process. Special attention is given to prototyping in the industry to support the design and testing of multimodal and multifunctional embedded systems.     

一种基于改进模拟退火算法的软硬件划分技术

提出一种应用于嵌入式系统软硬件划分的改进模拟退火算法.算法通过使用基于Cauchy分布的扰动模型和Tsallis接收准则来提高模拟退火算法的性能.通过对比经典的模拟退火软硬件划分技术以及实验结果的验证表明,使用改进模拟退火算法能加快划分的收敛,并且找到目标函数的最优值的概率也更大.     

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

In this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution.     

Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation

This paper presents a hardware/software co-design approachwhere different specification languages can be used in parallel, allowingeffective system co-modeling. The proposed methodology introduces a processmodel that extends the traditional spiral model so as to reflect the designneeds of modern embedded systems. The methodology is supported by an advancedtoolset that allows co-modeling and co-simulation using SDL, Statecharts andMATRIX_X, and interactive hardware/software partitioning. The effectivenessof the proposed approach is exhibited through two applicati on examples: thedesign of a car window lift mechanism, and the design of a MAC layer protocolfor wireless ATM networks.     

全定制软/硬件协同设计中的硬件优化技术

提出了基于单相似系统生成的软/硬件协同设计中的硬件优化技术.介绍了一种基于子图匹配软/硬件协同设计技术的大致框架,引进通用子图群合并算法,并着重讨论了基于节点压缩优化技术的高效子图群合并算法.实验结果很好地证明了所有上述理论的正确性以及算法的有效性.     

软硬件协同减少媒体处理器中寄存器文件写次数的方法

在嵌入式系统的应用中,程序代码中存在着相当多的局部变量,这些局部变量的使用范围(生存期)通常都很小.相关指令在流水中需要局部变量的值可以直接从旁路逻辑中得到,并在流水中完成局部变量值的全部使用.对这种局部变量就没有必要将流水输出结果写回寄存器文件,以减少对寄存器文件(RF)的读写操作次数,从而降低对寄存器文件端口的读写要求.决定是否将结果写回寄存器文件的关键的是要确定寄存器的生存期以及流水中旁路逻辑的情况,本文根据所设计的媒体处理器提出了一种确定程序代码中寄存器生存期的算法,并通过指令编码实现对硬件结构的使能控制,即对流水输出结果写回寄存器文件的控制.软件仿真结果表明,对DSP中不同的应用程序平均可以减少94%的寄存器文件写次数.     

基于关键路径和面积预测的软硬件划分方法

本文提出了一种基于关键路径和面积预测的软硬件划分方法,这种划分方法将软硬件映射和任务调度合而为一,在调度过程中同时完成软硬件的映射,充分发挥了任务调度的作用.在实验过程中,我们对比了基于模拟退火算法的软硬件划分方法(SA)和基于路径分析的软硬件划分方法(PA).实验结果表明,我们提出的方法在成功率以及结果的优化程度上都能取得更好的效果.     

软件复杂性与测试用例集价值

测试用例集价值是测试用例集的重要问题,本文给出了以复杂性度量为基础的测试用例集合价值度量模型,并在此度量基础上定义了三个重要的度量:测试密度,测试用例价值贡献以及测试用例集合执行相似度,并通过实际的例子指出了如何进行度量.     

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and processes with the objective of performance optimization with a limited hardware and software cost. We define the metric values for partitioning and develop a cost function that guides partitioning towards the desired objective. We consider minimization of communication cost and improvement of the overall parallelism as essential criteria during partitioning. Two heuristics for hardware/software partitioning, formulated as a graph partitioning problem, are presented: one based on simulated annealing and the other on tabu search. Results of extensive experiments, including real-life examples, show the clear superiority of the tabu search based algorithm.     

基于SharpDevelop构建T/R组件测试系统软件架构

介绍了T/R组件自动测试系统软件的发展趋势及基本要求,阐述了基于插件及插件系统进行软件开发的优点,重点研究开源IDE 软件SharpDevelop的原理及组成,探讨以SharpDevelop软件框架为基础来构建T/R组件自动测试系统软件架构,保证架构的通用性及可扩展性,更好地实现自动测试系统软件仪器驱动以及测试程序的扩展及移植。举例介绍了在此架构下如何开发T/R组件自动测试应用程序。     

基于软/硬件协同设计的嵌入式系统的性能测试

本文首先分析了传统的嵌入式系统设计方法及目前流行的软硬件协同设计的方法,指出软硬件协同设计方法是嵌入式领域的一个研究热点,接着分析了传统的测试方式的缺点,然后介绍了AMC公司的CodeTEST嵌入式软件在线分析与测试解决方案,同时也简要介绍了其它几种嵌入式测试工具。     

软/硬件协同设计方法学研究的现状与分析

通过简述集成电路工业的发展现状 ,引出软 /硬件协同设计方法学研究的重要性 ,并阐释了软 /硬件协同设计的主要概念。然后 ,着重介绍了目前各种有关国际成果和主流方向 ,并结合对相关领域问题的分析 ,深入分析了这些研究导向的共性与不足。最后以此为基础 ,试提出了“全定制”软 /硬件协同设计方法学所应遵循的一种建设性研究思路     

基于LabWindows/CVI的多线程测控软件设计技术

多线程技术是W in32操作系统的一项重要软件技术。CVI 6.0及其以后版本提供了线程池和异步定时器两种多线程运行机制,为测控软件的设计开发带来了一次技术飞跃。文中结合测控软件设计实例,详细介绍了在CVI平台下多线程编程技术的应用方法。     

Labwindows/CVI数据库技术在轻武器杀伤测试软件中的应用

在轻武器杀伤测试过程中由于测试条件多变、传感器易受损坏,需要经常对通道配置、传感器参数、测速靶型号进行更改。针对虚拟仪器开发平台Labwindows/CVI的数据库技术进行了详细的介绍,并结合实际应用需求,将数据库技术运用于测试软件中。测试结果表明,利用数据库技术可在保证稳定性的前提下提高软件灵活性和可扩展性。     

精密测距系统中频信号解算的仿真与验证

介绍了精密测距地面台标定设备中测距部分的组成及原理，描述了精密测距系统中的中频信号解算算法，并对算法进行了仿真和验证。     

基于BIST的编译码器IP核测试

介绍了用于IP核测试的内建自测试方法（BIST）和面向测试的IP核设计方法,指出基于IP核的系统芯片（SOC）的测试、验证以及相关性测试具有较大难度,传统的测试和验证方法均难以满足。以编译码器IP核为例,说明了基于BIST的编译码器IP核测试的基本实现原理和具体实现过程,通过加入测试外壳实现了对IP核的访问、隔离和控制,提高了IP核的可测性。     

基于1553B总线的仿真测试软件的设计与实现

主要阐述了1553B总线的特点,数据结构总线特性。结合Condor公司的PCMCIA接口的PCCARD-1553B板卡和支持此板卡的源代码级API函数,给出一个通用1553B总线接口总线控制器端仿真测试软件的设计思想、方法和详细过程。该软件已应用于对特定航电设备的测试工作,稳定可靠、适应性强,可满足不同的测试需求。