A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 $mu$m CMOS process and occupies an active chip area of 1.1 mm $^{2}$. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of ${-}$12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.      

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in th...     

A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.     

A highly linear receiver front-end employing modified derivative superposition method with tuned inductors for 5.25 GHz

We design a highly linear CMOS RF receiver front-end operating in the 5 GHz band using the modified derivative superposition (DS) method with one- or two-tuned inductors in the low noise amplifier (LNA) and mixer. This method can be used to adjust the magnitude and phase of the third-order currents at output, and thus ensure that they cancel each other out. We characterize the two front-ends by the third-order input intercept point (IIP3), voltage conversion gain, and a noise figure based on the TSMC 0.18 μm RF CMOS process. Our simulation results suggest that the front-end with one-tuned inductor in the mixer supports linearization with the DS method, which only sacrifices 1.9 dB of IIP3 while the other performance parameters are improved. Furthermore, the front-end with two-tuned inductors requires a precise optimum design point, because it has to adjust two inductances simultaneously for optimization. If the inductances have deviated from the optimum design point, the front-end with two-tuned inductors has worse IIP3 characteristic than the front-end with one-tuned inductor. With two-tuned inductors, the front-end has an IIP3 of 5.3 dBm with a noise figure (NF) of 4.7 dB and a voltage conversion gain of 23.1 dB. The front-end with one-tuned inductor has an IIP3 of 3.4 dBm with an NF of 4.4 dB and a voltage conversion gain of 24.5 dB. There is a power consumption of 9.2 mA from a 1.5 V supply.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS

This paper presents a 0.18-/spl mu/m CMOS direct-conversion IC realized for the Universal Mobile Telecommunication System (UMTS). The chip comprises a variable gain low-noise amplifier, quadrature mixers, variable gain amplifiers, and local oscillator generation circuits. The solution is based on very high dynamic range front-end blocks, a low-power superharmonic injection-locking technique for quadrature generation and continuous-time dc offset removal. Measured performances are an overall gain variable between 21 and 47 dB, 5.6 dB noise figure, -2 dBm out-of-band IIP3, -10 dBm in-band IIP3, 44.8-dBm minimum IIP2, and -155-dBc/Hz phase noise at 135 MHz from carrier frequency, while drawing 21 mA from a 1.8-V supply.     

A low power high-performance area efficient RF front-end exploiting body effect for 2.4 GHz IEEE 802.15.4 applications

The rising internet-of-things applications in home automation, smart wearables, healthcare monitoring demand small, area efficient, high-performance and low power radio frequency (RF) blocks for effective short-range communication. This growing market demand is addressed in this paper by proposing a fully CMOS radio frequency front-end (RFE) exploiting bulk effect. Apart from the primary function of frequency translation, proper circuit performance concerning the linearity, conversion gain, and noise figure is required for low-cost densely integrated transceivers operating in the 2.4 GHz ISM band. The proposed RFE at 2.4 GHz is designed and implemented in UMC 180 nm CMOS process technology with two modes of operation. In high gain mode (Mode-I), the post-layout simulation with SpectreRF shows a peak gain of 30.06 dB, IIP2 at 64.52 dBm, IIP3 at −2.74 dBm and a DSB-NF of 7.68 dB while consuming only 9.24 mW from the 1.8 V supply. In the high linear mode (Mode-II), the RFE achieves a higher IIP3 of 10.78 dBm, IIP2 of 91.56 dBm, the conversion gain of 23.5 dB, DSB-NF of 9.46 dB while consuming a low power of 3.6 mW. The fully CMOS circuit occupies a core area of only 0.0021 mm². The proposed front-end exhibits a spurious free dynamic range (SFDR) of 81.18 dB ensuring the high dynamic operation of the wireless system.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixer's IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.     

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

一种带有改进的25%占空比本振产生电路的WCDMA/GSM高线性度接收机射频前端分析与设计

本文提出了一种满足WCDMA/GSM系统要求的全集成接收机射频前端。WCDMA模式下无需声表面波滤波器。为了提高包括IP3和IP2指标在内的线性度性能,射频前端包括电容减敏的多栅低噪声放大器、带有本文提出的IP2校准电路的电流模式无源混频器以及似Tow-Thomas结构的双二阶可重构跨阻放大器。本文提出了一种新的低功耗、低相噪、可产生四相25%占空比本振信号的多模分频器。同时,本文通过采用带有片上电阻的恒定gm偏置电路,减小工艺和温度对转换增益的影响。本文中的射频前端电路集成在一个0.13um CMOS工艺下实现的带有片上频率综合器的接收机中。测试结果显示,在这个高线性度射频前端的帮助下,对于所有的模式和频带,接收机可以获得-6dBm的IIP3和至少 60dBm的IIP2。     

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems

A 0.13-mu m CMOS fourth-order notch filter for the rejection of the 5-6 GHz interference in UWB front-ends is reported. The filter is integrated into an analog front-end for Mode #1 UWB. A thorough analysis based on a simplified model of the filter is carried out. An algorithm for the automatic tuning and calibration of the filter is also discussed and demonstrated. Two versions of the circuit are designed and fabricated: the first comprises a low-noise amplifier and the filter, and the second expands it to a complete front-end. In the latter version the filter was also redesigned. The filter provides more than 35 dB of attenuation and has a tuning range of 900 MHz, adding less than 30% power consumption to the LNA. The out-of-band IIP3 (higher than -13.2 dBm with the filter off) takes a 9-dB advantage from the filter and the compression of the gain due to the out-of-band blocker is reduced by at least 6 dB in the complete front-end. The conversion gain of the front-end is 25 dB per channel, its average noise figure is lower than 6.2 dB, and its in-band 1-dB compression point is higher than - 30 dBm at a power consumption of 32 mW.     

应用于GSM/EDGE零中频接收机的CMOS射频前端

介绍了一个零中频接收机CMOS射频前端,适用于双带(900MHz/1800 MHz)GSM/EDGE;E系统.射频前端由两个独立的低噪声放大器和正交混频器组成,并且为了降低闪烁噪声采用了电流模式无源混频器.该电路采用0.13 μm CMOS工艺流片,芯片面积为0.9 mm×1.0 mm.芯片测试结果表明:射频前端在90...     

A 1.1 V 6.2 mW,wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5–6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below −8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm².     

A 1 GHz CMOS RF front-end IC for a direct-conversion wirelessreceiver

An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 μm CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers     

一个双频带可重构的直接变频接收机射频前端

A dual-band reconfigurable wireless receiver RF front-end is presented, which is based on the directconversion principle and consists of a low noise amplifer （LNA） and a down-converter. By utilizing a compact switchable on-chip symmetrical inductor, the RF front-end could be switched between two operation frequency bands without extra die area cost. This RF front-end has been implemented in the 180 nm CMOS process and the measured results show that the front-end could provide a gain of 25 dB and IIP3 of 6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm^2.     

A 5.25-GHz image rejection RF front-End Receiver With Polyphase filters

A 5.25-GHz image rejection (IR) radio frequency (RF) front-end receiver is proposed, which is implemented in 0.18-/spl mu/m CMOS technology. The proposed receiver adopts both a high-intermediate frequency (IF) and the double quadrature architecture to achieve high IR at 5-GHz frequency. The measured results show a power gain of 14 dB, a minimum noise figure of 7.9dB, and IIP3 of -8dBm. The measured maximum image rejection ratio is 45dBc. The receiver consumes a total of 32mA from a 1.8-V supply.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.