An integrated JK flip-flop circuit

An integrated JK flip-flop circuit, which is constructed using an RS flip-flop and four gates, is described. The circuit operation is based on an original concept, which is different from the conventional master-slave principle. Results of a monolithic integration using emitter-coupled logic (ECL) circuits are also given. As compared with the conventional master-slave-type JK flip-flop, which is constructed using ECL, a 40 percent improvement in speed-power product has been obtained.     

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297–298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.     

Logic gates with shaped Josephson junctions

Long (L//spl lambda//SUB j/>5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (/spl lambda//SUB j/ being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed sidelobes, providing good logic gain and permitting logic fan-in with multiple control lines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I/SUB G//spl sime/6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3/spl times/10/SUP -15/ J.     

Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

Dynamic effects in Josephson devices operated as logic gates

The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.     

Resistor-loaded high-speed sense circuit for Josephson memory

A design and experimental verification of a new high-speed sense circuit for Josephson memory are reported. This sense circuit consists of latching logic circuits with resistive loads and is able to adoptX-Ynonsequential access. It is necessary to decrease base-electrode capacitance of sense gates or to insert dummy inductors in the counter electrodes for the gate in order to realize high-speed memory circuit through word-line impedance matching. In 4-kbit RAM's, it was clarified that the gathering circuit which is composed of two-stage OR gates, each of which is composed of an 8-input wired RCL-OR gate, can minimize the gathering delay time. An experimental sense circuit was fabricated using a 5-µm Pb-alloy process, and the read-out time was measured to be about 400 ps using an on-chip sampling circuit.     

Logic operation at 5 Gb/s of an output interface for single-flux-quantum systems

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.     

光控单稳-双稳转换逻辑单元

用光电晶体管替换HEMT作为输入端,结合RTD可以构成新的光控逻辑单元,它具有光电流开关和自锁功能,该功能在实验及电路模拟中得到证实.在此基础上,若以异质结光电管(HPT)和RTD集成,可以设计和制作诸如D型触发器等不同功能的光控逻辑电路单元.     

光控单稳-双稳转换逻辑单元(英文)

用光电晶体管替换HEMT作为输入端,结合RTD可以构成新的光控逻辑单元,它具有光电流开关和自锁功能,该功能在实验及电路模拟中得到证实.在此基础上,若以异质结光电管(HPT)和RTD集成,可以设计和制作诸如D型触发器等不同功能的光控逻辑电路单元.     

光控单稳-双稳转换逻辑单元

用光电晶体管替换HEMT作为输入端,结合RTD可以构成新的光控逻辑单元,它具有光电流开关和自锁功能,该功能在实验及电路模拟中得到证实.在此基础上,若以异质结光电管(HPT)和RTD集成,可以设计和制作诸如D型触发器等不同功能的光控逻辑电路单元.     

Complementary Josephson-junction circuit: a fast flip-flop and logic gate

A logic circuit with Josephson junctions has been developed that operates as logic gate or as a flip-flop. Despite the latching-type characteristic of the Josephson tunnel junction, the complementary logic circuit is nonlatching. The test circuit has a power dissipation of 16.4 ?W and a signal risetime of approximately 60 ps has been measured.     

基于形状工程的可靠磁性逻辑器件和触发器实现

纳米级磁性逻辑器件是一种新兴的场耦合计算范例,可用于实现非易失性和极低功耗的磁性逻辑电路.然而,杂散磁场和温度波动热效应阻碍了器件和电路的可靠转换.该文研究了对称缺失等腰三角形特殊形状纳磁体的转换特性,提出了利用这种特殊形状纳磁体实现磁性逻辑器件可靠转换的方法.基于特殊形状纳磁体器件设计了流水线RS触发器时序电路,并采用OOMMF软件进行了性能模拟.结果表明,特殊形状纳磁体实现的基本触发器电路不但能够进行可靠的流水线计算,同时还具有较高的工作温度和良好的按比例缩小特征.     

An all DC-powered Josephson logic circuit

A novel DC-powered Josephson circuit is reported. An improved HUFFLE-type DC flip-flop with a parallel resistor, to prevent hang-up, is constructed by combinational circuits as well as sequential circuits. The basic device is a vertical type two-junction interferometer with only three-metal layers. The design rule is 2.5 μm. High junction-current density allows for a wide operating margin even with a low inductance load. Basic circuit function test elements have been completed. The DC flip-flop with excess gate current works as a GHz range VCO (voltage controlled oscillator) for internal clock generation. The speedup junction successfully accelerated the switching speed. The ring-oscillator showed a minimum gate delay of 11.3 ps     

Microthyristor-based sequential circuits and systems

This paper describes the construction of new circuit configurations for some sequential circuits. These circuits are based on the microthyristor as a microelectronic bistable device that can store logic one and logic zero and on NMOS transistors that act either as pass transistors or drivers. The shift register, considered as a main type of sequential circuit, is developed from a D flip-flop that is designed basically from the microthyristor as a bistable device. Moreover, different types of counters based on the microthyristor as a storing element are developed. Microthyristor sequential circuits were found to perform well.     

Superconductor integrated circuit fabrication technology

Today's superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.     

一种用于激光告警的PIN面阵探测系统设计

针对激光告警技术中面阵成像探测方式容易产生漏警、虚警以及信号处理难度大的问题,提出了一种基于触发器阵列锁存的PIN面阵探测系统设计方案。该系统以触发器为基本单元,同时在PIN面阵探测电路的输出端设计了信号锁存阵列,可将来自PIN面阵探测器所有通道的输出信号同步锁存,并设计了读取电路将锁存阵列中的面阵数据以串行数据的形式输出。采用FPGA搭建了阵列规模为8×8、角度分辨率为6°的信号锁存阵列和读取电路进行了试验验证,结果表明该方案可以实现高分辨率激光告警功能。     

Niobium-based integrated circuit technologies

Metallurgical and electrical properties of Nb and NbN films for use as Josephson junction electrodes and wiring layers are investigated. The crystallographic and superconducting properties necessary for Nb-based integrated circuit processes are clarified. Tunnel barrier structures of NbN-Nb oxide-NbN (Pb alloy) and Nb-Al oxide-Nb Josephson junctions have been analyzed and correlated with junction characteristics and critical current uniformity. It was found that the surface structure of a base electrode should be smooth to ensure that Josephson junctions have low leakage current and uniform critical current distribution. New types of Josephson junctions with artificial tunnel barriers such as amorphous Si or Mg oxide are reviewed. A variety of Josephson junction structures or processes have been developed for Nb-based Josephson integrated circuits in order to improve circuit performance. These include junction miniaturization, planarization, and stacked junction structures. These structures are mainly intended for Nb-Al oxide-Nb Josephson circuits. The Nb-Al oxide-Nb Josephson junction technology is by far the most advanced and has been used in logic and memory circuits, for example a 4-bit×4-bit parallel multiplier, a Josephson logic gate array, a 16-bit arithmetic logic unit, a 4-bit microprocessor, and 1-kb and 4-kb memory circuits     

Optical input/output interface system for Josephson junctionintegrated circuits

An optical input/output interface system for a Josephson junction integrated circuit is fabricated and tested. The system consists of a superconducting optical detector, a dc powered Josephson circuit, a dc powered Josephson high voltage circuit, a liquid-He-cooled semiconductor amplifier, and a liquid-He-cooled semiconductor laser. Features of the system are use of an ultrathin NbN film for the optical detector and adoption of the dc powered Josephson circuits for logic operation circuits. Correct optical output signal is detected by a liquid-He-cooled semiconductor photodiode. The optical input/output interface has the advantage of low heat penetration and low crosstalk compared to the interface using conventional coaxial lines. Moreover, dc powered Josephson circuits have an advantage of low crosstalk from power supply lines compared to conventional Josephson circuits, which are driven by ac supply current     

A DC-powered Josephson logic family that uses hybrid unlatchingflip-flop logic elements (Huffles)

This paper describes the development of a dc-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles). The Huffle circuit used in this study is modified by adding a parallel resistor to the original Hebard-type Huffle circuit. Analysis of the circuit's operation shows that the undesirable hung-up phenomena are prevented by this modification. Based on the result of the analysis, the circuit's parameters are derived and a typical operating margin of ±26% is obtained. Besides AND/OR operations using a threshold logic operation, two-input exclusive OR (XOR), two-input multiplexor (MUX), and three-input majority (MAJ) operations are realized using a Huffle gate in which 2-Josephson-interferometers (2JI) in the standard Huffle gate are replaced by stacked-2JI's. Thus, a Huffle logic family, formed from NOT, AND, OR, XOR, MUX, MAJ, and flip-flop (FF), are constructed. By using this Huffle logic family, a 6-b arithmetic logic operating unit (ALU), a 6-b analog-to-digital converter (ADC), and a 6-b gray-to-binary converter (GBC) have been successfully operated. During high-speed testing, a 1-b comparator was operated up to an input bandwidth of 6 GHz