Monte Carlo optimization of superconducting complementary outputswitching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix     

Weakly superconducting circuits

An equivalent circuit has been developed for the time-dependent dissipating state of superconductivity which accompanies quantum phase slip. This equivalent circuit is used here to analyze the superconducting thin-film ring magnetometer and to determine its operating characteristics in terms of measurable circuit parameters.     

Self-timed logic circuits

Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of these techniques are presented with illustrations from practical development projects. Some of the key principles behind self-timed operation are reviewed. Design tools to enable complex practical applications to be engineered are considered. For engineers who wish to find out more a selection of key references is provided     

Digital logic circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed     

Dynamic logic CMOS circuits

A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.     

Self-biasing Josephson logic circuits

A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation.     

Proposal of single-flux-quantum logic device

A new type of logic gate that can be designed using a nonhysteretic Josephson weak link is proposed. The basic component of the proposed device is a one-junction interferometer, and a logic state is represented by either a zero or a single-flux-quantum. In contrast to the "Parametric Quantron," this device is designed to operate without a three-phase clock and the dependence of the junction critical current on magnetic field is not used. The switching behavior of the device was simulated by computer and an analytical expression for the switching delay has been obtained.     

Josephson nonlatching logic circuits

The authors describe nonlatching logic circuits that can be designed using Josephson junctions as the switching elements. The circuits require no current resetting and can be switched between their two logic states with a subnanosecond delay time. The switching behavior has been simulated numerically. The choice of parameters and junction types is analyzed. The distinctive features which make these circuits attractive are discussed.     

All-refractory Josephson logic circuits

A process for the fabrication of Josephson integrated circuits is described which uses only refractory materials. The Josephson devices are Nb-Si-Nb tunnel junctions which are formed in the initial phase of the process. After depositing a Nb-Si-Nb `trilayer' over the entire substrate, the individual devices are isolated by the selective niobium anodization process (SNAP). Other materials used are molybdenum for the normal resistors and bias-sputtered SiO/SUB 2/ for additional insulator layers. The process uses only five photolithographic steps to produce circuits of the direct-coupled isolation type. This simplicity is achieved by using some layers for multiple purposes and by fabricating components with different functional purposes in a single step. For example, the lower electrode of the Josephson devices also functions as the ground plane and the contacts to the ground plane are actually large-area Josephson junctions formed simultaneously with the active devices. Low capacitance junctions (~0.025 pF//spl mu/m/SUP 2/) are produced with good uniformity.     

Reliability evaluation of logic circuits

An important guide in the project of logic circuits is the ability to estimate rightly its reliability. In this paper a new type of analysis is presented, by following the references [1], [2], [3] and the method implemented by [4]. This is applicable to all logic circuits, combinational or sequential and by this new structure a reliability matrix is obtained.     

Characterization of integrated logic circuits

The characterization of integrated logic circuits must be accomplished in a manner which fully accounts for the circuit's nonlinear behavior and is amenable to experimental verification. The approach taken in this paper is to describe both the dc and the transient performance of the circuit by developing nonlinear equivalents of the 2-port "black box" parameters used in specifying linear networks. Such terminal parameter characterization has the obvious advantage of eliminating the need to probe the integrated circuit for testing purposes. In addition, knowledge of terminal performance is a necessity when the circuit is studied from a system point of view. In this paper an emitter-coupled logic circuit is used as an example to illustrate the analysis techniques. After accomplishing the terminal parameter characterization of this circuit, attention is directed towards using these results to establish a design procedure. To this end the relationship that exists between power consumption and the circuit safety margins is explored, and the minimum power-delay time product is derived. The analysis accounts for the parasitics which are present in a monolithic integrated circuit and illustrates the use of the nonlinear transistor model.     

Comparison of MOSFET logic circuits

Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.     

Current-mode CMOS multiple-valued logic circuits

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described     

Feedthrough in emitter-coupled logic circuits

Emitter coupled logic circuits transient noise behavior is examined. The mechanisms and causes of feedthrough are analyzed using, first, approximate expressions and, second, an accurate model. The experimental observations of feedthrough give ample evidence of good agreement between the theoretical and computational results. An accurate appraisal of the causes of feedthrough, such as C/SUB b//SUB e/, C/SUB b//SUB c/, c/SUB i//SUB d/, C/SUB i//SUB t/, C/SUB p/, and C/SUB c//SUB u//SUB s/ determine the main factors that offer scope for improvement.     

Dynamic-type CMOS four-valued logic circuits

We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given.     

Cumulative balance testing of logic circuits

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation, provably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

Precharged CMOS quaternary logic encoder-decoder circuits

Multiple-valued buses have been proposed as a way of overcoming the interconnection complexity of VLSI. In this paper we present efficient new encoder-decoder circuits for four-valued bus signalling in clocked CMOS VLSI systems. The important advantages of our designs are that they can be implemented by standard binary CMOS processes, and are considerably simpler than earlier designs. Furthermore, they have no static power dissipation. The circuits have been extensively simulated using SPICE and have been found to operate reliably.