基于GPU的AES算法实现

近几年图形处理器GPU的通用计算能力发展迅速,现在已经发展成为具有巨大并行运算能力的多核处理器,而CUDA架构的推出突破了传统GPU开发方式的束缚,把GPU巨大的通用计算能力解放了出来.本文利用GPU来加速AES算法,即利用GPU作为CPU的协处理器,将AES算法在GPU上实现,以提高计算的吞吐量.最后在GPU和CPU...     

高级加密标准AES候选算法的比较

通过了AES第2轮选拔的MARS、RC6TM、Rijndael、Serpent、TwoFish5种加密算法,每种算法各有千秋．作者从多种角度对以上5种算法进行比较,分析了各自的优缺点．     

基于FPGA的AES算法的实现

介绍了高级加密标准( AES,Advanced Encryption Standard)算法的原理,设计了一个能够实现初始密钥128位、192位和256位可选的AES加解密算法系统,以适应多种使用环境.实验结果表明了基于现场可编程门阵列(FPGA)可编程逻辑器件的实现方法提供了并行处理能力,达到设计所要求的处理性能基准.整个设计具有很强的实用性,运行稳定,且效果良好,可以被广泛应用于网络,文件等安全系统.     

AES密码算法的FPGA实现与仿真

通过对高级加密标准AES算法进行描述,给出了基于FPGA设计的具体设计流程和方法。采用多轮加密过程共用一个轮运算的顺序结构。由于文中的加密模块与解密模块采用相关且不同的初始密钥和不同的密钥扩展模块,结果加强了通信的安全性。采用16位并行总线数据结构,利用16位输入128输出的 FIFO 数据缓存器对输入数据进行缓存,从而完成数据的加解密。最后通过 ISE 13.1仿真验证了该算法设计的正确性。     

高级加密标准AES候选之一--MARS算法

本文对MABS算法进行了详细介绍．描述了MABS算法的加解密过程及子密钥生成过程．     

AES算法在流媒体加密中的应用

文中在分析高级加密标准AES算法原理的基础上，探讨了采用AES加密算法针对实时流媒体进行加密的具体实现，最后文中提出了一种流媒体安全传输系统中保持共享缓冲区的读写同步机制．     

AES/Rijndael算法协处理器设计与实现

AES／Rijndael算法是高性能的加密算法，具有极佳的抗攻击性能。文章提出了AES／Rijndael算法协处理器的半定制ASIC硬件实现方案，设计兼顾了处理速度与硬件资源耗费。其较高的加密强度，对于保护关键信息的安全具有很强的实用价值。方案在Cyclone系列FPGA芯片上实现，占用逻辑单元1400余个，综合仿真和实测的结果验证了本设计的正确性。     

AES算法的密码分析与快速实现

高级加密标准(AES)确定分组密码Rijndael为其算法,取代厂泛使用了20多年的数据加密标准(DES),该算法将在各行业各部门获得广泛的应用.文章以DES为参照对象,阐述了Rijndael算法的设计特色,介绍了AES在密码分析方面国内外已有的一些理论分析成果,描述了AES算法采用软件和硬件的快速实现方案.     

基于FPGA的AES算法芯片设计实现

高级加密标准(AES)集安全性、高效性、灵活性于一身,研究其硬件实现具有很重要的应用价值.本文针对AES分组密码算法的结构特点,讨论了AES算法FPGA实现的优势,重点分析了加/脱密模块的实现方案,最后给出在Quartus Ⅱ下的仿真实验结果.     

AES密码算法的VLSI实现

给出AES轮加密结构,详细分析MixColumns模块功能,提出基于VLSI实现的方案。用移位寄存器和异或单元代替有限域乘法模块,简化了电路的规模。在子密钥产生模块中,提出了根据密钥长度设计不同模块的方法,加快了芯片运行速度。     

Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

A low-power and low-cost advanced encryption standard (AES) coprocessor is proposed for Zigbee system-on-a-chip (SoC) design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and deeryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine (FSM) and clock gating (CG) technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor (CMOS) technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz,and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.     

抗差分功耗分析和差分故障分析的AES算法VLSI设计与实现

提出了一种抗差分功耗分析和差分故障分析的AES算法硬件设计与实现方案,该设计主要采用了数据屏蔽和二维奇偶校验方法相结合的防御措施.在保证硬件安全性的前提下,采用将128bit运算分成4次32bit运算、模块复用、优化运算次序等方法降低了硬件实现成本,同时使用3级流水线结构提高了硬件实现的速度和吞吐率.基于以上技术设计的AES IP核不仅具有抗双重旁道攻击的能力,而且拥有合理的硬件成本和运算性能.     

High-speed VLSI architectures for the AES algorithm

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2/sup 4/) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.     

Programmable VLSI cubic-like function implementation

An analogue VLSI implementation of a cubic-like function is presented, whose design is focused to reduce the circuit complexity. Simulations show that the V-I characteristic of the circuit resembles a cubic function, which can be easily adjusted by changing the bias parameters     

VLSI implementation of pulse activated synapses

A generic circuit, the pulse stimulated charge pumping (PSCP) synapse, is presented. The PSCP synapse is a device based on charge pumping of interface states: it produces at its output a charge packet proportional to the number of pulses applied to its input, and to the electrically programmed density of interface states. It is particularly suitable for realising artificial neural networks in which the neuron activity is implemented as a pulse train, closely resembling the behaviour of biological neural networks. The PSCP synapse can be realised easily in less than 50 mu m/sup 2/, and has a large dynamic range. Preliminary experimental results are presented showing the current against frequency behaviour of the device, for various densities of interface states.<>     

VLSI implementation of discrete wavelet transform

This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N×10⁶ samples/s corresponding to a clock speed of N MHz     

多模式雷达信号源设计与实现

基于DDS理论,设计并实现了多模式雷达信号源。可以灵活产生LFM、NLFM、单频、相位编码等多种脉冲信号波形,能有效验证脉冲压缩与信号处理单元的工作性能。测试结果满足系统要求。     

Design and VLSI implementation of QMF banks

The authors consider the design of multirate filterbanks for applications such as subband coding with IIR QMF (quadrature mirror filter) pairs. These offer reduced complexity and low latency at the expense of the loss of exact linear phase. In particular, consideration is given to the use of all-pass sections where linear phase is approximately achieved by being part of the objective in numerical optimisation experiments. This approach compares favourably with previous IIR based approaches. Finite wordlength design using simulated annealing shows that low coefficient wordlength may be used. This leads to efficient realisations with three-port adaptors. Using pipelining implementation, a flexible VLSI architecture is designed that can be used for a variety of subband decompositions. Layout and simulation of the design have been performed.