A study of mottling phenomenon on textured multicrystalline silicon wafers and its potential effects on solar cell performance

The mottling phenomenon refers to the appearance of irregular dark patterns on HF–HNO₃ acid etching textured multicrystalline silicon (mc-Si) wafers. The mottles have been identified as clusters of dislocation etch pits. In the acidic texturization, conditions favoring light reflectivity reduction usually lead to enhanced mottling. In a belief of adverse effect of the mottles to cell performance, light reflectivity reduction is more or less compromised in industry to avoid the mottling. The present study aims to identify whether appearance of the mottles alone really adversely affects the wafers minority carrier lifetime. Both serial examinations of an acid etched mc-Si wafer sample and parallel examinations of neighboring pairs of mc-Si wafer samples etched in acids of different HF/HNO₃ ratios were carried out. The results show that development of the mottling, i.e., growth of dislocation etch pits, does not deteriorate mc-Si wafers in their minority carriers lifetime; rather it even slightly increases the lifetimes. Light reflectivity measurement and modeling show that the mottles can contribute to reduction of light reflectivity, and ~3% relative reduction of reflectivity is expected for multicrystalline silicon wafers of ordinary level of dislocation density. Removal of the defected zone surrounding a dislocation by the etching is postulated as a reason for the observed mottling-enhancement of the lifetime. It is further postulated that, in texturization of mc-Si wafers for cell production, instead of compromising light reflectivity reduction to avoid the mottling, it may be better to pursue lower light reflectivity, allowing some extent of the mottling. Meanwhile, more attention should be paid to compatibility of the cone-shaped dislocation etch-pit with grid printing of solar cells.     

Plasma etching of different polydimethylsiloxane elastomers, effects from process parameters and elastomer composition

Plasma etching of three different polydimethylsiloxane elastomers has been studied. One elastomer was a commercially available kit (Sylgard-184) and the other two were made by mixing individual components. The etching was done in a multi-wafer tool. The process gas used in the etching was a mixture of SF₆ and O₂. The etch rate was measured as a function of pressure for all three materials at the centre and the edge of the etched structures. It was found that fillers in the elastomer reduces the etch rate but has little effect on the shape of the etched surface. Second, it was found that excess of chain ends in the elastomer gives larger changes in the shape of the etched surface, as pressure changes. Third, it was found that loading (reduction of etch rate) is significant in the presence of dummy silicon wafers compared to glass wafers.     

碱性腐蚀工艺条件对硅片表面腐蚀形貌的影响

碱性腐蚀工艺条件对硅片表面腐蚀形貌如粗糙度、显微镜下的表面状况的影响做了研究,通过实验结果给出了特定要求条件下硅片腐蚀的最佳方案.运用硅的化学腐蚀机理分析了表面腐蚀状况的原因.     

Etch characteristics of KOH, TMAH and dual doped TMAH for bulk micromachining of silicon

High precision bulk micromachining of silicon is a key process step to shape spatial structures for fabricating different type of microsensors and microactuators. A series of etching experiments have been carried out using KOH, TMAH and dual doped TMAH at different etchant concentrations and temperatures wherein silicon, silicon dioxide and aluminum etch rates together with <100> silicon surface morphology and <111>/<100> etch rate ratio have been investigated in each etchant. A comparative study of the etch rates and etched silicon surface roughness at different etching ambient is also presented.From the experimental studies, it is found that etch rates vary with variation of etching ambient. The concentrations that maximize silicon etch rate is 3% for TMAH and 22 wt.% for KOH. Aluminum etch rate is high in KOH and undoped TMAH but negligible in dual doped TMAH. Silicon dioxide etch rate is higher in KOH than in TMAH and dual doped TMAH solutions. The <111>/<100> etch rate ratio is highest in TMAH compared to the other two etchants whereas smoothest etched silicon surface is achieved using dual doped TMAH. The study reveals that dual doped TMAH solution is a very attractive CMOS compatible silicon etchant for commercial MEMS fabrication which has superior characteristics compared to other silicon etchants.     

Bulk micromachining of silicon in TMAH-based etchants for aluminum passivation and smooth surface

The fabrication of silicon based micromechanical sensors often requires bulk silicon etching after aluminum metallization. All wet silicon etchants including ordinary undoped tetramethyl ammonium hydroxide (TMAH)-water solution attack the overlaying aluminum metal interconnect during the anisotropic etching of (100) silicon. This paper presents a TMAH-water based etching recipe to achieve high silicon etch rate, a smooth etched surface and almost total protection of the exposed aluminum metallization. The etch rate measurements of (100) silicon, silicon dioxide and aluminum along with the morphology studies of etched surfaces are performed on both n-type and p-type silicon wafers at different concentrations (2, 5, 10 and 15%) for undoped TMAH treated at various temperatures as well as for TMAH solution doped separately and simultaneously with silicic acid and ammonium peroxodisulphate (AP). It is established through a detailed study that 5% TMAH-water solution dual doped with 38 gm/l silicic acid and 7 gm/l AP yields a reasonably high (100) silicon etch rate of 70 μm/h at 80 °C, very small etch rates of SiO₂ and pure aluminum (around 80 Å/h and 50 Å/h, respectively), and a smooth surface (±7 nm) at a bath temperature of 80 °C. The etchant has been successfully used for fabricating several MEMS structures like piezoresistive accelerometer, vaporizing liquid micro-thruster and flow sensor. In all cases, the bulk micromachining is carried out after the formation of aluminum interconnects which is found to remain unaffected during the prolonged etching process at 80 °C. The TMAH based etchant may be attractive in industry due to its compatibility with standard CMOS process.     

The effect of cathode materials on reactive ion etching of silicon and silicon dioxide in a CF4 plasma

Silicon and silicon dioxide have been Reactive Ion Etched in a CF₄ plasma using a diode sputtering configuration to achieve etching. Pressures ranged from 20 to 100 millitorr and power densities to the RF cathode were between 0.1 and 1.0 W/cm². The effect of cathode material on the quality of etched surfaces and on etch rates has been investigated. It has been observed that the etch rate of silicon decreases as the area of silicon exposed to the plasma is increased and that this silicon loading effect is strongly influenced by the material covering the balance of the cathode. For instance, the silicon loading effect is much more pronounced when silicon dioxide rather than aluminum is used to cover the balance of the cathode. This silicon loading effect was investigated further by varying RF power. It was found that loading a silicon dioxide covered cathode with silicon wafers decreases the dependence of silicon etch rate on power. The silicon dioxide etch rate and its dependence on RF power are the same whether silicon, silicon dioxide or aluminum is used to cover the balance of the cathode. Possible explanations for these experimental results will be discussed.     

Electron beam induced current investigations of active electrical defects in silicon due to reactive ion etching and reactive ion beam etching processes

Reactive ion etching and reactive ion beam etching are common tools for anisotropic etch processes in silicon microdevice fabrication; but, unfortunately, they also create radiation damage in the etched surface. We have studied the electrically active defects by measuring the recombination of carriers with the help of the electron beam induced current (EBIC) mode of a secondary electron microscope. We have measured the temperature behavior of the samples by annealing studies and the temperature dependent EBIC signal for several p-doped silicon wafers and obtained different shaped curves. Theoretical EBIC models developed with the assumption of a reduced net carrier concentration in the etched areas agree with our experimental results.     

多晶黑硅表面微结构对电池效率的影响

采用Ag离子辅助化学刻蚀法制备了多晶黑硅薄片,使用NaOH溶液处理多晶黑硅表面,增大其表面纳米孔直径,使SiNx薄膜能够均匀覆盖整个黑硅表面,提高黑硅的钝化效果,进而提高多晶黑硅电池光电转化效率.通过反射谱仪、扫描电子显微镜(SEM)、太阳电池测试系统等测试和表征不同扩孔时间对多晶黑硅各方面性能的影响.结果表明:未被NaOH扩孔处理的多晶黑硅的反射率最低,为5.03％,多晶黑硅太阳电池的光电转化效率为16.51％.当多晶黑硅被NaOH腐蚀40 s时,反射率为10.01％,电池的效率为18.00％,比普通多晶硅太阳电池的效率高2.19％,比未被扩孔处理的多晶黑硅太阳电池的效率高1.49％.     

Uniform pyramid formation on alkaline-etched polished monocrystalline (100) silicon wafers

Pyramidal texturing of monocrystalline silicon using alkaline etchants depends strongly upon the initial condition of the wafer surface and upon etching parameters. Texturization of polished wafers is often incomplete, with non-textured areas arising to yield high values of reflectance. A new technique is introduced for uniform pyramid formation on polished wafers. Nitrogen is used to expel dissolved oxygen in the etch solution, since it has been observed that oxidizing agents act to encourage polished etch surfaces.     

Metal-Assisted Chemical Etching Using Tollen’s Reagent to Deposit Silver Nanoparticle Catalysts for Fabrication of Quasi-ordered Silicon Micro/Nanostructures

Metal-assisted chemical etching (MacEtch) of semiconductor materials in HF/H₂O₂ solution using noble-metal particles as catalysts has gained much attention in the past few years due to its unique properties. In this work, nanoscale Ag particles were deposited on (100) and (111) surfaces of polished p-Si wafers through the silver-mirror reaction. Subsequently these wafers were etched in 1:1:1 (v:v:v) HF(49%):H₂O₂(30%):EtOH solution at ambient temperature and pressure for 12 h, producing a number of different quasi-ordered silicon micro/nanostructures. The resulting surface-modified wafers exhibited mixed micro- and nanostructures that are an inherent feature of the etch process; for example, steps appear on the sidewalls of crystallographically defined nanopores, because the catalytic Ag nanoparticles are convected as they transit the developing pore during the etching process. The resulting materials exhibited much reduced reflectivity, reaching a maximum of 3.7× reduction near 330 nm, which renders them of interest in potential applications such as back-reflector templates for deposition of thin-film solar cell materials.     

Efficient nanostructured ‘black’ silicon solar cell by copper‐catalyzed metal‐assisted etching

We produce low‐reflectivity nanostructured ‘black’ silicon (bSi) using copper (Cu) nanoparticles as the catalyst for metal‐assisted etching and demonstrate a 17.0%‐efficient Cu‐etched bSi solar cell without any vacuum‐deposited anti‐reflection coating. The concentration ratio of HF to H₂O₂ in the etch solution provides control of the nanostructure morphology. The solar‐spectrum‐weighted average reflection (R_ave) for bSi is as low as 3.1% on Cu‐etched planar samples; we achieve lower reflectivity by nanostructuring of micron‐scale pyramids. Successful Cu‐based anti‐reflection etching requires a concentration ratio [HF]/[H₂O₂] ≥ 3. Our 17.0%‐efficient Cu‐etched bSi photovoltaic cell with a pyramid‐texture has a R_ave of 3% and an open circuit voltage (V_oc) of 616 mV that might be further improved by reducing near‐surface phosphorus (P) densities. Copyright © 2014 John Wiley & Sons, Ltd.     

Microfabrication of ultra-long reinforced silicon neural electrodes

The authors describe a simple dry-etch silicon microfabrication process to develop an array of electrodes with multiple recording sites suitable for neural recording applications. This new high-yield fabrication process uses commercially available ultra-thin silicon wafers as substrate material. A xenon difluoride system is used to etch the silicon substrate to form the electrode structures. The novel concept of structural reinforcement to produce elongated and reliable probe electrodes is introduced. The authors demonstrate recording silicon electrodes that can reach lengths longer than 10 mm having only 50 μm thicknesses and an 100 μm average width. This new microfabrication process illustrates a simple, cost-effective and mass-producible method for developing ultralong silicon probes for deep brain implantation and neural recording.     

The influence of oxidation-sirtl etch condition on the stacking fault generation in (111) silicon wafers

The successive oxidation-Sirtl etch technique has been investigated to evaluate the perfection of silicon crystals by detecting extrinsic stacking faults produced during oxidation. Experiments were performed in (111) epitaxial wafers. Measured densities of stacking faults were found to epend on the conditions of thermal oxidation, and stacking fault densities were a maximum at an oxidation temperature of around 1100°C. The stacking fault densities were reduced appreciably when epitaxial wafers were chemically etched to remove several tens of microns prior to the test. The generation of stacking faults is thought to occur by heterogeneous nucleation due to a very small amount of unidentified impurity found in epitaxial crystals.     

X-ray reflectivity of silicon on insulator wafers

The ability of X-ray reflectivity to analyse different silicon on insulator structures is underlined. The standard geometry with first reflection occurring at the surface gives information about the thickness, roughness, and density of the layers. Deeply buried interfaces, i.e. in between thick wafers, are analysed with a non-standard geometry (the first reflection occurs at the buried interface) and with a high-energy radiation. These two methods are, respectively, illustrated by the reflectivity measurements of (SiO₂/Si/SiO₂|bulk Si) and (bulk Si/thermal SiO₂|native SiO₂/bulk Si) bonded structures, and are explained in the framework of kinematic theory of X-ray reflectivity.     

多晶Si太阳电池新型制绒工艺研究

提出一种采用二次酸腐蚀的多晶Si制绒新方法,首先在HF/HNO3的富HNO3体系中对Si片进行一次腐蚀,之后在富HF体系中进行二次腐蚀,以优化表面织构,减少光在Si表面的反射损失。制绒后,用扫描电子显微镜(SEM)对Si片进行了表面形貌分析,用Carry 5000紫外-可见-近红外分光光度计测量反射谱线,得到未镀减反射膜(ARC)的二次腐蚀制绒的最低反射率为20.34%,比一次腐蚀制绒(22.70%)低2.36%。将二次腐蚀新工艺应用于太阳电池工业制备中,对电池输出参量进行检测分析。结果表明,经过二次腐蚀工艺处理的太阳电池开路电压(VOC)、短路电流(JSC)和效率η均比采用一次腐蚀工艺的太阳电池有不同程度的提高,制成的太阳电池最高效率为14.93%。     

Process design for plasma etching of polysilicon/silicon nitride/polysilicon sandwich structures for sensor applications

An in situ two-step process has been developed for plasma etching of poly-Si/silicon nitride/poly-Si sandwich structures for a surface micromachined tactile sensor. The first step of the process uses a CF₄-based gas mixture to etch the upper poly-Si layer and the second uses a CHF₃-based gas mixture to etch the silicon nitride with an etching selectivity of three over the lower poly-Si layer. Both the upper poly-Si and the silicon nitride of the sandwich structure can be etched with the same photoresist mask, while the lower poly-Si layer remains relatively un-etched. Compared with a one-step process which uses the same chemistry as in step one of the two-step process, the two-step process provides the desired etch selectivity, better uniformity and process tolerance.     

Stack system of PECVD amorphous silicon and PECVD silicon oxide for silicon solar cell rear side passivation

A stack of hydrogenated amorphous silicon (a‐Si) and PECVD‐silicon oxide (SiO_x) has been used as surface passivation layer for silicon wafer surfaces. Very good surface passivation could be reached leading to a surface recombination velocity (SRV) below 10 cm/s on 1 Ω cm p‐type Si wafers. By using the passivation layer system at a solar cell's rear side and applying the laser‐fired contacts (LFC) process, pointwise local rear contacts have been formed and an energy conversion efficiency of 21·7% has been obtained on p‐type FZ substrates (0·5 Ω cm). Simulations show that the effective rear SRV is in the range of 180 cm/s for the combination of metallised and passivated areas, 120 ± 30 cm/s were calculated for the passivated areas. Rear reflectivity is comparable to thermally grown silicon dioxide (SiO₂). a‐Si rear passivation appears more stable under different bias light intensities compared to thermally grown SiO₂. Copyright © 2008 John Wiley & Sons, Ltd.     

Device characteristics of amorphous indium-gallium-zinc-oxide channel capped with silicon oxide passivation layers

It was investigated how the amorphous indium-gallium-zinc-oxide (a-IGZO) channel of a back-gate of thin film transistor (TFT) is affected by the deposition of silicon oxide layers on their top surfaces by radio frequency magnetron sputtering. Preliminary investigations showed that the deposition of silicon oxide layer caused damages to the surfaces of pristine silicon wafers resulting in substantial roughening. However, bombardments by the energetic particles involved in the sputtering process seem to have played beneficial roles in that the a-IGZO channel TFTs showed improved performances in respect of the carrier density, field effect mobility, and on-off current ratio. Such improvements are attributed to the modification of the a-IGZO channel to decrease the concentration of oxygen vacancy sites and/or to average the oxygen vacancy sites thereby increasing the carrier concentrations and decreasing the density of trap sites, as revealed in the negative shift of the threshold voltage. On the other hand, such channel modification by the passivation process resulted in the slight increase in the subthreshold swing. It is suggested that the a-IGZO channel TFTs can be passivated by simple sputtering process without etch stop layer since the process rather improved the device performances despite some damages to the passivated surfaces.     

Analysis for load limitation of square-shaped silicon diaphragms

Influences of residual stress on mechanical properties of boron-doped silicon diaphragms are analyzed. Considering the residual stress, the total stress analytical solutions for square-shaped boron-doped silicon diaphragms with small deflection and large deflection are presented. It is found that the residual stress should not be neglected in calculation of the total stress for diaphragms with large ratio of edge length to thickness. The load limitation P_max of the square-shaped boron-doped silicon diaphragms is calculated based on the total stress analytical solution and the Griffith fracture criterion. The results agree well with the reported experiments. Many micro-etch-holes were found on the surface of boron-doped silicon diaphragm made from wet etch process, and these holes cause great degradation of the load limitation P_max compared with perfect crystal silicon diaphragms.     

Contamination of silicon and oxidized silicon wafers during plasma etching

Neutron activation analysis has been used to study the type and level of contamination of silicon and oxidized silicon wafers exposed to various plasmas used in silicon device processing. Silicon wafers exposed to plasmas in a reactor previously used to remove SiN passivation layers from Au metallized wafers were found to be heavily contaminated with Au (up to ∼10¹⁴ atoms/cm²). Au contamination of oxidized silicon wafers similarly treated was two to three orders of magnitude smaller regardless of whether SiO₂ etched faster or slower than Si in the plasmas used. Wet chemical cleaning of contaminated Si subsequent to plasma exposure was relatively ineffective in removing residual Au. This is interpreted as indicating indiffusion of Au during plasma exposure of Si. Exposure to a polymer forming plasma reduced the level of Au contamination of Si by nearly two orders of magnitude due to effective “sealing” of reactor surfaces by polymer film. Further, the level of contamination of Si was observed to decrease by over two orders of magnitude with usage time of the reactor during a 300-day time period when no Au containing materials were introduced into the reactor.