Characteristics of ZnOV2O5MnO2Nb2O5Er2O3 semiconducting varistors with sintering processing

The effects of sintering temperature on the microstructure, electrical properties, and dielectric characteristics of ZnOV₂O₅MnO₂Nb₂O₅Er₂O₃ semiconducting varistors have been studied. With increase in sintering temperature the average grain size increased (4.5–9.5 μm) and the density decreased (5.56–5.45 g/cm³). The breakdown field decreased with an increase in the sintering temperature (6214–982 V/cm). The samples sintered at 900 °C exhibited remarkably high nonlinear coefficient (50). The donor concentration increased with an increase in the sintering temperature (0.60×10¹⁸–1.04×10¹⁸ cm^?3) and the barrier height exhibited the maximum value (1.15 eV) at 900 °C. As the sintering temperature increased, the apparent dielectric constant increased by more than four-fold.     

Non-ohmic effect and pulse aging behavior of V/Mn/Co/Bi/Dy co-doped ZnO semiconducting varistors with sintering processing

We examined the effect of sintering on the microstructure, non-ohmic properties, clamping characteristics, and pulse aging behavior of V/Mn/Co/Bi/Dy codoped ZnO semiconducting varistors. The average grain size increased from 4.7 to 10.4 µm and the densities of the sintered pellets decreased from 5.47 to 5.37 g/cm³ with the increase in sintering temperature. The maximum non-ohmic coefficient (35.3) was obtained at a sintering temperature of 900 °C. Varistors sintered at 900 °C exhibited the best clamp characteristics, a clamp voltage ratio of 1.74–2.54 at a pulse current of 1–25 A. Varistors sintered at 925 °C exhibited the strongest electrical stability; variation rates for the breakdown field measured at 1.0 mA/cm², for the non-ohmic coefficient, and for the leakage current density were 3.4%, 6.6%, and −11.2%, respectively, after application of a pulse current of 100 A.     

Aging characteristics of ZnO–V2O5-based varistors for surge protection reliability

The effect of sintering temperature on clamping characteristics and pulse aging behavior of V₂O₅/MnO₂/Nb₂O₅ co-doped zinc oxide varistors was systematically investigated at 875–950 °C. Experimental results related to varistor effect showed that the breakdown field decreased dramatically from 6830 to 968 V/cm with the increase in the sintering temperature and the non-ohmic coefficient exhibited a maximum (49.5) at 900 °C in the sintering temperature. Varistors sintered at 900 °C exhibited the best clamp characteristics for the pulse current of 1–100 A, with the clamp voltage ratio of K = 1.86–2.77. Varistors sintered at 875 °C exhibited the strongest stability; variation rates for the breakdown field, for the non-ohmic coefficient, and for the leakage current density were −14.2%, −63.6%, and 59.0%, respectively, after application of a multi-pulse current of 100 A.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Ultra-low-energy ion-beam-synthesis of Ge nanocrystals in thin ALD Al2O3 layers for memory applications

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al₂O₃ layers before and after implantation of Ge ions (1 keV, 0.5–1 × 10¹⁶ cm^?2) and thermal annealing at temperatures in the 700–1050 °C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO₂-rich layer at the Al₂O₃/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ～5 nm inside the implanted Al₂O₃ layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al₂O₃ layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al₂O₃ layers.     

Fabrication of the flexible pentacene thin-film transistors on 304 and 430 stainless steel (SS) substrate

Flexible organic thin-film transistors (OTFT) were fabricated on 304 and 430 stainless steel (SS) substrate with aluminum oxide as a gate insulator and pentacene as an organic semiconductor. Chemical mechanical polishing (CMP) process was used to study the effect of the SS roughens on the dielectric properties of the gate insulator and OTFT characteristics. The surface roughness was decreased from 33.8 nm for 304 SS and 19.5 nm for 430 SS down to ～2.5 nm. The leakage current of the metal–insulator–metal (MIM) structure (Au/Al₂O₃/SS) was reduced with polishing. Mobility and on/off ratio of pentacene TFT with bare SS showed a wide range of values between 0.005 and 0.36 cm²/Vs and between 10³ and 10⁵ depending on the location in the substrate. Pentacene TFTs on polished SS showed an improved performance with a mobility of 0.24–0.42 cm²/Vs regardless of the location in the substrate and on/off ratio of ～10⁵. With self assembled monolayer formation of octadecyltrichlorosilane (OTS) on insulator surface, mobility and on/off ratio of pentacene TFT on polished SS was improved up to 0.85cm²/Vs and ～10⁶. I–V characteristics of pentacene TFT with OTS treated Al₂O₃/304 SS was also obtained in the bent state with a bending diameter (D) of 24, 45 or 70 mm and it was confirmed that the device performed well both in the linear regime and the saturation regime.     

A facile chemical reduction approach for effectively tuning thermoelectric properties of PEDOT films

Poly(3,4-ethylenedioxythiophene)–tosylate–polyethylene glycol–polypropylene glycol–polyethylene glycol (PEDOT–Tos–PPP) films were prepared via a vapor phase polymerization (VPP) method. The films possess good electrical conductivity (1550 S cm⁻¹), low Seebeck coefficient (14.9 μV K⁻¹) and thermal conductivity (0.501 W m⁻¹ K⁻¹), and ZT ∼ 0.02 at room temperature (RT, 295 K). Then, the films were treated with NaBH₄/DMSO solutions of different NaBH₄ concentrations to adjust the redox level. After the NaBH₄/DMSO treatment (dedoping), the electrical conductivity of the films continuously decreased from 1550 to 5.7 S cm⁻¹, whereas the Seebeck coefficient steeply increased from 14.9 to 143.5 μV K⁻¹. A maximum power factor of 98.1 μW m⁻¹ K⁻² has been achieved at an optimum redox level. In addition, the thermal conductivity of the PEDOT–Tos–PPP films decrease from 0.501 to 0.451 W m⁻¹ K⁻¹ after treated with 0.04% NaBH₄/DMSO solution. A maximum ZT value of 0.064 has been achieved at RT. The electrical conductivity and thermal conductivity (Seebeck coefficient) of the untreated and 0.04% NaBH₄/DMSO treated PEDOT–Tos–PPP films decrease (increases) with increasing temperature from 295 to 385 K. And the power factor of the films monotonically increases with temperature. The ZT at 385 K of the 0.04% NaBH₄/DMSO treated film is 0.155.     

Phase transition and surface morphology effects on optical,electrical and lithiation/delithiation behavior of nanostructured Ce-doped V2O5 thin films

Cerium doped V₂O₅ thin films were prepared by the sol−gel process. X-ray diffraction analysis revealed the phase transition from α-V₂O₅ orthorhombic to β-V₂O₅ tetragonal structure by annealing at 400 °C. The SEM and AFM images revealed that annealing temperature changed the surface morphology of the V₂O₅ films from fiber like wrinkle network to elongated sheets. Also, the particle shape was significantly influenced by Ce doping and a nanorod-like morphology was formed at 1.5 mol% Ce−doped V₂O₅. Power spectral density analysis indicated that surface roughness and fractal dimension of β−V₂O₅ increase by Ce doping. Optical measurement showed that the band gap narrowing (from 2.68 to 2.28 eV) occurred when the annealing temperature and dopant concentration increased. The variation of activation energy of the films was explained based on the small polaron hopping mechanism. The α−V₂O₅ film showed enhanced lithium−ion storage capacity compared to pristine β−V₂O₅ film and 1 mol% Ce−doped α−V₂O₅ thin film revealed the best ion storage capacity (Q_a=207.19 mC/cm², I_max=4.13 mA/cm² at scan rate of ν=20 mV/s).     

Properties of In2O3 films obtained by thermal oxidation of sprayed In2S3

In₂S₃ thin films were grown by the chemical spray pyrolysis (CSP) method using indium chloride and thiourea as precursors at a molar ratio of S:In=2.5. The deposition was carried out at 350 °C on quartz substrates. The film thickness is about 1 µm. The films were then annealed for 2 h at 550, 600, 650 and 700 °C in oxygen flow. This process allows the transformation of nanocrystal In₂O₃ from In₂S₃ and the reaction is complete at 600 °C. X-ray diffraction spectra show that In₂O₃ films are polycrystalline with a cubic phase and preferentially oriented towards (222). The film grain size increases from 19 to 25 nm and RMS values increase from 9 to 30 nm. In₂O₃ films exhibit transparency over 70–85% in the visible and infrared regions due to the thickness and crystalline properties of the films. The optical band gap is found to vary in the range 3.87–3.95 eV for direct transitions. Hall effect measurements at room temperature show that resistivity is decreased from 117 to 27 Ω cm. A carrier concentration of 1×10¹⁶ cm^?3 and mobility of about 117 cm² V^?1 s^?1 are obtained at 700 °C.     

Effect of nano Al2O3 particles doping on electromigration and mechanical properties of Sn–58Bi solder joints

In the present study, the effect of Al₂O₃ nanoparticles on performances of Sn–58Bi solder were investigated in aspects of electro-migratio, shear strength and microhardness. The experimental results show that the Al₂O₃ nanoparticles significantly improved microstructure and mechanical performances of solder joints. With the addition of 0.5 wt% Al₂O₃, the intermetallic compounds (IMC) reduced from 2.5 μm to 1.27 μm after 288 aging hours at 85 °C. Furthermore, after electromigration test under a current density of 5 × 10³ A/cm² at 85 °C, Bi-rich layers formed at the anode side of both Al₂O₃ doped and plain solder. Moreover, the addition of Al₂O₃ nanoparticles reduced the mean thickness of Bi-rich layer. In addition, the growth rate of the IMC layer of Al₂O₃ doped solder decreased by 8% compared with the plain solder. Besides, the Al₂O₃ doped solder exhibited better performance than plain solder in microhardness after different aging times. While, the addition of Al₂O₃ significantly impeded the degradation of the shear strength of solder joint after aging for 48 and 288 h. Furthermore, it was worth noting that the fracture surface of doped solder showed a typical rough and ductile structure. However, plain solder exhibited a relatively smooth and fragile surface.     

Low-voltage,high-performance n-channel organic thin-film transistors based on tantalum pentoxide insulator modified by polar polymers

Polar polymers (polyfluorene copolymers, PFN–PBT) with different polarities are utilized to modify the surface of tantalum pentoxide (Ta₂O₅) insulator in n-channel organic thin-film transistors (OTFTs). A high mobility of 0.55 cm²/Vs, high on/off current ratio of 1.7 × 10⁵, and low threshold voltage of 2.8 V are attained for the OTFT with the modification polymers, the performances of which are much better than those of OTFT with only Ta₂O₅ insulator. The performances of the OTFT with only Ta₂O₅ insulator are only 0.006 cm²/Vs in mobility, 5 × 10³ in on/off ratio, and 12.5 V in threshold voltage. Furthermore, it is found that the threshold voltage of the OTFTs with PFN–PBT modification layer is easily tuned by polarities of the polymers. Further studies show that self-assembly dipole moments in the polymers play an important role in the improvement of the OTFT performances.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

Improvement of 1.53 μm emission and energy transfer of Yb3+/Er3+ co-doped tellurite glass and fiber

To improve the 1.53 μm band emission of Er³⁺, the trivalent Yb³⁺ ions were introduced into the Er³⁺ single-doped tellurite glass with composition of TeO₂–ZnO–La₂O₃, a potential gain medium for Er³⁺-doped fiber amplifier (EDFA). The improved effects were investigated from the measured 1.53 μm band and visible band spontaneous emission spectra together with the calculated 1.53 μm band stimulated emission (signal gain) spectra under the excitation of 975 nm laser diode (LD). It was found that Yb³⁺/Er³⁺ co-doping scheme can remarkably improve the visible band up-conversion and the 1.53 μm band fluorescence emission intensity, and meanwhile improves the 1.53 μm band signal gain to some extent, which were attributed to the result of the effective energy transfer of Yb³⁺:²F_5/2 + Er³⁺:⁴I_15/2 → Yb³⁺:²F_7/2 + Er³⁺:⁴I_11/2. The quantitative study of energy transfer mechanism was performed and microscopic energy transfer parameters between the doped rare-earth ions were determined. In addition, the spectroscopic properties of Er³⁺ were also investigated from the measured absorption spectrum according to the Judd–Ofelt theory, and the structure behavior and thermal stability of the prepared tellurite glass were analyzed based on the X-ray diffraction (XRD) and differential scanning calorimeter (DSC) measurements, respectively.     

Fabrication of single crystal field-effect transistors with phenacene-type molecules and their excellent transistor characteristics

Single crystal field-effect transistors (FETs) using [6]phenacene and [7]phenacene show p-channel FET characteristics. Field-effect mobilities, μs, as high as 5.6 × 10^?1 cm² V^?1 s^?1 in a [6]phenacene single crystal FET with an SiO₂ gate dielectric and 2.3 cm² V^?1 s^?1 in a [7]phenacene single crystal FET were recorded. In these FETs, 7,7,8,8-tetracyanoquinodimethane (TCNQ) was inserted between the Au source/drain electrodes and the single crystal to reduce hole-injection barrier heights. The μ reached 3.2 cm² V^?1 s^?1 in the [7]phenacene single crystal FET with a Ta₂O₅ gate dielectric, and a low absolute threshold voltage |V_TH| (6.3 V) was observed. Insertion of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F₄TCNQ) in the interface produced very a high μ value (4.7–6.7 cm² V^?1 s^?1) in the [7]phenacene single crystal FET, indicating that F₄TCNQ was better for interface modification than TCNQ. A single crystal electric double-layer FET provided μ as high as 3.8 × 10^?1 cm² V^?1 s^?1 and |V_TH| as low as 2.3 V. These results indicate that [6]phenacene and [7]phenacene are promising materials for future practical FET devices, and in addition we suggest that such devices might also provide a research tool to investigate a material’s potential as a superconductor and a possible new way to produce the superconducting state.     

Low-operating-voltage polymeric transistor with solution-processed low-k polymer/high-k metal-oxide bilayer insulators

We have successfully demonstrated a polymeric semiconductor-based transistor with low-k polymer/high-k metal-oxide (TiO₂) bilayer as gate dielectric. The TiO₂ layers are readily processable from solution and cured at low temperature, instead of traditionally sputtering or high temperature sintering process, thus may suitable for a low-cost organic field effect transistors (FETs) manufacture. The low-k polymer capped on TiO₂ layer could further smooth the TiO₂ dielectric surface and suppress the leakage current from grain boundary of TiO₂ films. The resulting unpatented P3HT-OFETs could operate with supply voltage less than 10 V and the mobility and threshold voltage were 0.0140 cm²/V s and 1.14 V, respectively. The on/off ratio was 1.0 × 10³.     

Characterization of MIS structures and thin film transistors using RF-sputtered HfO2/HIZO layers

MIS structures using HfO₂ and HIZO layers, both deposited by room temperature RF magnetron sputtering are fabricated for TFTs application and characterized using capacitance-voltage. The relative dielectric constant obtained at 1 kHz was 11, the charge carrier concentration of the HIZO was in the range of (2–3) × 10¹⁸ cm^− 3 and the interface trap density at flat band was smaller than 2 × 10¹² cm^− 2. The critical electric field of the HfO₂ layer was higher than 5 × 10⁵ V/cm, with a current density in the operating voltage range below 4 × 10^− 8 A/cm². The hysteresis and bias stress behavior of RF-sputtered HfO₂/HIZO MIS structures is presented. Fabricated HfO₂/HIZO TFTs worked in the operation voltage range below 8 V.     

Experimental study for high effective mobility with directly deposited HfO2/La2O3 MOSFET

We experimentally examine the effective mobility in nMOSFETs with La₂O₃ gate dielectrics without SiO_x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N_s = 5 × 10¹¹ cm^?2 in the low 10¹¹ cm^?2 eV^?1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.     

Enhancing pyroelectric and ferroelectric properties of PVDF composite thin films by dispersing a non-ferroelectric inclusion La2O3 for application in sensors

Thin films consisting of non-ferroelectric inclusions of La₂O₃ dispersed in a polymer matrix of polyvinylidene difluoride (PVDF) were prepared by the spin-coating method. It was found that the pyroelectric coefficient and remanent polarization of the composites were significantly improved to reach 42 μC/m² K and 84 mC/m², respectively. The enhancement of the measured coefficients in the composites can be achieved by introducing a very small amount (3 wt%) of La₂O₃. The figure of merit for material sensitivity, F_D has also improved from 69 to 86 μC/m² K¹. A local field in the inclusion site was shown to facilitate the poling procedure. A simple Maxwell–Wagner model in which the dc conductivity of the inclusion site was taken into consideration showed a good agreement with the obtained pyroelectric and ferroelectric properties.     

On the current conduction mechanisms of CeO2/La2O3 stacked gate dielectric

It was found that the electrical properties of CeO₂/La₂O₃ stack are much better than a single layer La₂O₃ film. A thin CeO₂ capping layer can effectively suppress the oxygen vacancy formation in the La₂O₃ film. This work further investigates the current conduction mechanisms of the CeO₂ (1 nm thick)/La₂O₃ (4 nm thick) stack. Results show that this thin stacked dielectric film still has a large leakage current density; the typical 1−V leakage can exceed 1 mA/cm² at room temperature. The large leakage current should be due to both the oxide defect centers as well as the film structure. Results show that at low electric field (<0.2 MV/cm), the thermionic emission induced current conduction in this stacked structure is quite pronounced as a result of interface barrier lowering due to the capping CeO₂ film which has a higher k value than that of the La₂O₃ film. At higher electric fields, the current conduction is governed by Poole–Frenkel (PF) emission via defect centers with an effective energy level of 0.119 eV. The temperature dependent current–voltage characteristics further indicate that the dielectric defects may be regenerated as a result of the change of the thermal equilibrium of the redox reaction in CeO₂ film at high temperature and the drift of oxygen under the applied electric field.