Novel design techniques for noise-tolerant power-gated CMOS circuits

In this paper we have investigated the single phase sleep signal modulation technique, step-wise V_gs technique and the three-phase reactivation technique to evaluate the noise characteristics of multi-threshold CMOS circuits used in communication systems. The stacking technique is also implemented in this paper for the sleep transistor. The stacking approach helps to minimize leakage power. The mode transition noise minimization techniques have been applied to 32-bit dynamic TSPC adder with stacked sleep transistors in a standard 45-nm CMOS process. The reactivation noise, delay and energy consumption of all the three techniques have been evaluated. It has been shown that the three phase modulation technique significantly minimizes the reactivation delay when the peak noise level is maintained the same for all three techniques. The three phase modulation technique shows 67.3% and 35% reduction in delay compared to the single phase and step-wise V_gs modulation techniques respectively. The reactivation energy is also suppressed by 49.3% and 39.14% with respect to the single-phase and stepwise V_gs techniques.     

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

As the size of CMOS devices is scaled down to lower the power consumption and space occupied on the chip to the nano-scale, unfortunately, noise is not reduced accordingly. As a result, interference due to noise can significantly affect circuit performance and operation. Since noises are random and dynamic in nature, probabilistic noise-tolerant approaches are more desirable to handle this problem. However, trade-offs between hardware complexity and noise-tolerance are severe design challenges in the probabilistic-based noise-tolerant approaches. In this paper, we proposed a cost-effective common-feedback probabilistic-based noise-tolerant VLSI circuit based on Markov random field (MRF) theory. We proposed a common latch feedback method to lower the hardware complexity. To further enhance the noise-tolerant ability, the common latch feedback technique is combined with Schmitt trigger. To demonstrate the proof-of-concept design, a 16-bit carry-lookahead adder was implemented in the TSMC 90 nm CMOS process technology. As compared with the state-of-art master-and-slave MRF design, the experimental results show that not only the transistor count can be saved by 20%, the noise-tolerant performance can also be enhanced from 18.1 dB to 24.2 dB in the proposed common feedback MRF design.     

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, power, and dynamic noise margin. A design methodology for skewed CMOS pipelined circuits has been developed. To demonstrate the applicability of the proposed logic style, 0.35 /spl mu/m 5.56 ns CMOS 16/spl times/16 bit multipliers have been designed using skewed logic circuits and fabricated through MOSIS. Measurement results show that the multiplier only consumed a power of 195 mW due to its low clock load.     

Efficient reliability evaluation methodologies for combinational circuits

Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.     

Channel ion implantation for small-geometry high-performance CMOS-SOS circuits

This paper describes an experimental study of channel ion implantation for optimization of small-geometry (1-1.5 µm) n- and p-channel silicon-on-sapphire (SOS) MOSFET's for high-performance CMOS applications. The influence of a wide range of channel implantation conditions on device characteristics are reported, and optimum channel doping profiles identified. Adequate performance of NMOS devices is achieved by the use of double boron channel implants, but excellent PMOS devices are obtained by the use of very lightly doped near-intrinsic device islands.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models.Delay, power consumption and the Power-Delay Product (PDP) in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35 μm, 0.18 μm and 90 nm CMOS technology considering different design targets, i.e., minimum power consumption, PDP, Energy-Delay Product (EDP) and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort.     

Band-pass correlation filter for illumination- and noise-tolerant face recognition

The paper proposes a band-pass correlation filter in frequency domain for frontal face recognition task under both poor illumination and noisy condition. The band-pass nature of the proposed filter is achieved through combination of a modified high-pass filter and a continuous wavelet filter. An optimal range of scale is selected for this wavelet filter. The performance of the proposed band-pass correlation filter for face recognition tasks under variations in illumination and noise is evaluated and compared with other filters using standard databases (YaleB and PIE). High recognition accuracy is achieved in this proposed technique.     

集成化故障检测电路设计

讨论了高频 (微波 )通讯系统中故障检测电路设计的一般方法及设计中应注意的问题 ,并给出了一个设计实例     

Design methodologies for reliability of SSL LED boards

This work presents a comparison of various LED board technologies from thermal, mechanical and reliability point of view provided by an accurate 3-D modelling. LED boards are proposed as a possible technology replacement of FR4 LED boards used in 400 lumen retrofit SSL lamps. Presented design methodology can be used for other high power SSL lamp designs. The performance of new LED board designs were evaluated by numerical modeling. Modeling methodology was proven by measurement on reference FR4 LED board. Thermal performance was compared by extracting of LED boards thermal resistances and thermal stress has been inspected considering the widest temperature operating range according to standards (−40 to +125 °C). Thermo-mechanical and reliability analysis have been performed to study parameters of each LED board technology, using thermal boundary conditions extracted from the thermal simulation of a whole LED lamp. Elastic–plastic analysis with temperature dependent stress–strain material properties has been performed. The objective of the work is to optimize not only the thermal management by thermal simulation of LED boards, but also to find potential problems from mechanical failure point of view and to present a methodology to design SSL LED boards for reliability.     

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOSand MTCMOS technologies

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic     

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

In this paper, we proposed a reliable ultra-low-voltage low-power latch design based on the probabilistic-based Markov random field (MRF) theory ,  and  to greatly improve the ability of noise-tolerance. Through MRF mapping decomposition, we map the previous state and the current state compatible logic function of the latch into the MRF network separately. In this way, we can overcome the challenge of applying Markov random field theory to sequential noise-tolerant circuits. In order to further lower the hardware cost and circuit complexity of the chip, we apply the absorption law and H-tree logic combination techniques [4] to simplify the circuit complexity of the MRF noise-tolerant latch circuit. To preserve the noise tolerant capability of MRF latch, we utilize the cross-coupled latching mechanism in the output of MRF latch. Finally, we apply the proposed MRF latch design in a 16-bit carry-lookahead adder circuit. In TSMC 90 nm CMOS process, our proposed circuit can operate reliably under a lower supply voltage of 0.55 V with superior noise tolerance and consumes only 31 μW power, which is 59.2% lower as compared with the conventional CMOS latch design.     

Design issues for high-performance active routers

Modern networks require the flexibility to support new protocols and network services without changes in the underlying hardware. Routers with general-purpose processors can perform data path packet processing using software that is dynamically distributed. However, custom processing of packets at link speeds requires immense computational power. This paper proposes a design of a scalable, high-performance active router. Multiple network processors with cache and memory on a single application specific integrated circuit are used to overcome the limitations of traditional single processor systems. The proposed design is used as a vehicle for studying the key issues that must be resolved to allow active networking to become a mainstream technology. Benchmark measurements are used to put the design in relation to actual application demands     

Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V_gs self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 μm partially-depleted SOI CMOS technology, the static power consumption at 200 °C is reduced by nearly three orders of magnitude at the expense of increased delay and area.     

混合电路电磁兼容设计与实例

在设计电子产品时,除了满足特定的功能要求外,还必须考虑产品的电磁兼容性,这对产品的质量和性能技术指标起着非常关键的作用。本文主要介绍了PCB设计时一些常用的解决电磁兼容性问题的措施,主要包括PCB布局、PCB布线、电源与地、时钟信号等方面的电磁兼容设计。并结合具体的工程实例进行说明分析。     

Design for reliability of generic sensor interface circuits

Numerous applications require the use of robust and reliable integrated circuits. In order to develop such circuits, a wide variety of influences need to be considered and also compensated if necessary. For a complete consideration of all reliability issues, the circuit has to be investigated on different levels of abstraction and together with the complete overlying system. These requirements are addressed in this work by using cross-layer design methods for the development of a generic sensor interface as an example for a complex integrated circuit. During the development, a reliability-aware design is used and major physical effects are taken into account, which alter the overall behavior of the system. Furthermore, modeling techniques are applied to port influences and circuit components from one level of abstraction to another. Possible countermeasures and compensation techniques for a reliable circuit design are also analyzed on transistor and system level. The result is a sensor interface circuit, which can be used to investigate all effects of interest and suitable countermeasures on different abstraction levels.     

Design of CMOS circuits for stuck-open fault testability

A CMOS design that offers highly testable CMOS circuits is presented. The design requires a minimal amount of extra hardware for testing. The test phase for the proposed design is simple and uses a single test vector to detect a fault. The design offers the detection of transistor stuck-open faults deterministically. In this design, the tests are not invalidated due to timing skews/delays, glitches, or charge redistribution among the internal nodes