Origin of void defects in Hg1−xCdxTe grown by molecular beam epitaxy

Characterization of defects in Hg_1−xCd_xTe compound semiconductor is essential to reduce intrinsic and the growth-induced extended defects which adversely affect the performance of devices fabricated in this material system. It is shown here that particulates at the substrate surface act as sites where void defects nucleate during Hg_1−xCd_xTe epitaxial growth by molecular beam epitaxy. In this study, we have investigated the effect of substrate surface preparation on formation of void defects and established a one-to-one correlation. A wafer cleaning procedure was developed to reduce the density of such defects to values below 200 cm⁻². Focal plane arrays fabricated on low void density materials grown using this new substrate etching and cleaning procedure were found to have pixel operability above 98.0%.     

Effect of oval defects in GaAs on the reliability of SiNx metal–insulator–metal capacitors

In this paper, we will assess the reliability of extrinsic defects in SiN_x metal–insulator–metal (MIM) capacitors as part of a GaAs high voltage (HV) FET process. The epitaxial GaAs layers used for this process contain a density of oval defects. Since the SiN_x is deposited at low temperatures, the MIM capacitors are amorphous and will always contain a certain amount of extrinsic defects. It will be shown that the number of extrinsic defects depends on the presence of the oval defects in the epitaxial GaAs layers. The reliability assessment will be done using electric field breakdown (Ebd), time dependent dielectric breakdown (TDDB) measurements and visual inspection. It will be shown that this combination can lead to an estimate of the lifetime and screening of capacitors containing extrinsic defects.     

Evaluation of the influence of an embedded porous silicon layer on the bulk lifetime of epitaxial layers and the interface recombination at the epitaxial layer/porous silicon interface

Porous silicon plays an important role in the concept of wafer‐equivalent epitaxial thin‐film solar cells. Although porous silicon is beneficial in terms of long‐wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron‐doped (10¹⁶/cm³) epitaxial layers grown on reorganised porous silicon as well as on pristine mono‐crystalline, Czochralski, p⁺ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p⁺ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p⁺ substrate interface (S ≅ 10³ cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.     

Progress in the Molecular Beam Epitaxy of HgCdTe on Large-Area Si and CdZnTe Substrates

This paper presents the progress in the molecular beam epitaxy (MBE) growth of HgCdTe on large-area Si and CdZnTe substrates at Raytheon Vision Systems. We report a very high-quality HgCdTe growth, for the first time, on an 8 cm × 8 cm CdZnTe substrate. This paper also describes the excellent HgCdTe growth repeatability on multiple 7 cm × 7 cm CdZnTe substrates. In order to study the percentage wafer area yield and its consistency from run to run, small lots of dual-band long-wave infrared/long-wave infrared triple-layer heterojunction (TLHJ) layers on 5 cm × 5 cm CdZnTe substrates and single-color double-layer heterojunction (DLHJ) layers on 6-inch Si substrates were grown and tested for cutoff wavelength uniformity and micro- and macrovoid defect density and uniformity. The results show that the entire lot of 12 DLHJ-HgCdTe layers on 6-inch Si wafers meet the testing criterion of cutoff wavelength within the range 4.76 ± 0.1 μm at 130 K and micro- and macrovoid defect density of ≤50 cm⁻² and 5 cm⁻², respectively. Likewise, five out of six dual-band TLHJ-HgCdTe layers on 5 cm × 5 cm CdZnTe substrates meet the testing criterion of cutoff wavelength within the range 6.3 ± 0.1 μm at 300 K and micro- and macrovoid defect density of ≤2000 cm⁻² and 500 cm⁻², respectively, on the entire wafer area. Overall we have found that scaling our HgCdTe MBE process to a 10-inch MBE system has provided significant benefits in terms of both wafer uniformity and quality.     

Quantitative Comparison Between Dislocation Densities in Offcut 4H-SiC Wafers Measured Using Synchrotron X-ray Topography and Molten KOH Etching

Molten KOH etching and x-ray topography have been well established as two of the major characterization techniques used for observing as well as analyzing the various crystallographic defects in both substrates and homoepitaxial layers of silicon carbide. Regarding assessment of dislocation density in commercial wafers, though the two techniques show good consistency in threading dislocation density analysis, significant discrepancy is found in the case of basal plane dislocations (BPDs). In this paper we compare measurements of BPD densities in 4-inch 4H-SiC commercial wafers assessed using both etching and topography methods. The ratio of the BPD density calculated from topographic images to that from etch pits is estimated to be larger than 1/sinθ, where θ is the offcut angle of the wafer. Based on the orientations of the defects in the wafers, a theoretical model is put forward to explain this disparity and two main sources of errors in assessing the BPD density using chemical etching are discussed.     

Properties of p +-n structures with a buried layer of radiation-induced defects

The p ⁺-n structures based on n-type Si with dopant density 1.7×10¹³–1.2×10¹⁴ cm⁻³ were irradiated with ²³⁸Pu α particles. A layer containing radiation-induced defects with a density of the order of 3×10¹³ cm⁻³ was produced at a depth of 20 μm. This defect density gave rise to intense draining of nonequilibrium carriers in the injection-extraction regime with stationary injection as well as with pulsed generation by single particles. This makes it possible to treat the damaged layer as a plane, introduced into the bulk, with an infinite surface recombination rate. The radiation-induced defects also participated in decreasing the conductivity. A characteristic space charge distribution and, correspondingly, a bias dependence of the capacitance are observed in the structure under reverse bias. Despite the presence of formally three charge regions, four sections appear on the capacitance curve. This latter effect is due to the “additional” charge step arising in the contact potential difference field and is characteristic of compensated deep levels in semiconductors. Fiz. Tekh. Poluprovodn. 32, 359–365 (March 1998)     

Surface‐Dominated Transport Properties of Silicon Nanowires

Surface effects are widely recognized to significantly influence the properties of nanostructures, although the detailed mechanisms are rarely studied and unclear. Herein we report for the first time a quantitative evaluation of the surface‐related contributions to transport properties in nanostructures by using Si nanowires (NWs) as a paradigm. Critical to this study is the capability of synthesizing SiNWs with predetermined conduction type and carrier concentration from Si wafer of known properties using the recently developed metal‐catalyzed chemical etching method. Strikingly, the conductance of p‐type SiNWs is substantively larger in air than that of the original wafer, is sensitive to humidity and volatile gases, and thinner wires show higher conductivity. Further, SiNW‐based field‐effect transistors (FETs) show NWs to have a hole concentration two orders of magnitude higher than the original wafer. In vacuum, the conductivity of SiNWs dramatically decreases, whereas hole mobility increases. The device performances are further improved by embedding SiNW FETs in 250 nm SiO₂, which insulates the devices from atmosphere and passivates the surface defects of NWs. Owing to the strong surface effects, n‐type SiNWs even change to exhibit p‐type characteristics. The totality of the results provides definitive confirmation that the electrical characteristics of SiNWs are dominated by surface states. A model based on surface band bending and carrier scattering caused by surface states is proposed to interpret experimental results. The phenomenon of surface‐dependent transport properties should be generic to all nanoscale structures, and is significant for nanodevice design for sensor and electronic applications.     

Easy-to-use surface passivation technique for bulk carrier lifetime measurements on silicon wafers

A novel, easily applicable surface passivation technique is presented, which, in combination with contactless photocoductance decay (PCD) measurements, allows a quick estimation of the bulk carrier lifetime of crystalline silicon wafers. The proposed passivation technique requires neither a chemical pre-cleaning of the silicon wafer nor expensive instrumentation. On both surfaces of the wafer a thin varnish film is deposited using a spinner. Subsequently, both surfaces of the coated silicon wafer are charged by means of a corona chamber. Using microwave-detected PCD measurements, we experimentally demonstrate that this novel surface passivation scheme provides differential surface recombination velocities in the 30–70 cm s⁻¹ range on p-as well as n-type silicon wafers. © 1998 John Wiley & Sons, Ltd.     

Shunt types in crystalline silicon solar cells

Nine different types of shunt have been found in state‐of‐the‐art mono‐ and multicrystalline solar cells by lock‐in thermography and identified by SEM investigation (including EBIC), TEM and EDX. These shunts differ by the type of their I–V characteristics (linear or nonlinear) and by their physical origin. Six shunt types are process‐induced, and three are caused by grown‐in defects of the material. The most important process‐induced shunts are residues of the emitter at the edge of the cells, cracks, recombination sites at the cell edge, Schottky‐type shunts below grid lines, scratches, and aluminum particles at the surface. The material‐induced shunts are strong recombination sites at grown‐in defects (e.g., metal‐decorated small‐angle grain boundaries), grown‐in macroscopic Si₃N₄ inclusions, and inversion layers caused by microscopic SiC precipitates on grain boundaries crossing the wafer. Copyright © 2004 John Wiley & Sons, Ltd.     

Structure and carrier lifetime in LT-GaAs

The relationship between the structural quality of low-temperature GaAs layers and the photoexcited carrier lifetime has been studied. Transmission electron microscopy, x-ray rocking curves, time-resolved reflectance methods, and photoconductive-switch-response measurements were used for this study. For a variety of samples grown at temperatures in the vicinity of 200°C, subpicosecond carrier lifetimes were observed both in as-grown layers, as well as in the same layers after post-annealing and formation of As precipitates. These results suggest that the carrier lifetime, which was found to be shorter in the as-grown layers than in the annealed ones, might be related to the density of As_Ga antisite defects present in the layers. The annealed layers which contained structural defects before annealing appeared to exhibit the longest carrier lifetime due to gettering of As on these defects (and formation of relatively large As precipitates) and depletion of extra As (As_Ga) defects from the layer. It was found as well that the responsivity of detectors fabricated on these layers depended strongly on the structural quality of the layers, with the greatest response obtained not for the layers with the fewest defects, but for the layers with 10⁷–10⁸/cm² of pyramidal defects.     

Low frequency noise measurements on silicon-on-sapphire (SOS) MOS transistors

Measurements of the equivalent input noise are performed on P-channel silicon-on-saphire, metal-oxide-semiconductor (SOSMOS) transistors as a function of the silicon layer bias voltage with respect to the source. Devices are operated in the ohmic region of the characteristics so that the results are easier to analyse. The results show a high degree of dispersion in the noise characteristics for the different tested devices all originated from the same silicon on sapphire wafer. We conclude that a dispersion of the silicon-sapphire interface properties, such as SRH centers density or fixed positive charge, exists on the wafer. From one specific device, we calculate a fixed positive silicon-sapphire interface charge (about 4 × 10¹¹ cm^?2) and a high density (about 5 × 10¹¹ cm^?2) SRH centers localized near the silicon-sapphire interface.     

Evaluation of super-critical thickness strained-Si on insulator (sc-SSOI) substrate

Crystal quality and strain distribution in SOI layer of conventional strained-Si on insulator (SSOI) and super-critical thickness strained-Si on insulator (sc-SSOI) were evaluated by in-plane X-ray diffraction (XRD), Raman spectroscopy, and other techniques. The surface defect distribution measured by wafer inspection system shows pit-type and line defects in both SSOI layers. More specifically, the sc-SSOI material has more line defects than conventional SSOI layers. Cross-hatched pattern defects were observed using X-ray topography (XRT) measurements. Raman mapping of 300 mm wafers shows the strain at the center of the wafer is larger than at the edge. In magnified close-up mapping, cross-hatched contrasts corresponding to misfit dislocations are observed, while the surface morphology is completely smoothed out. In-plane XRD measurements show the strain depth variations are quite uniform along the depth direction. The full width at half maximum (FWHM) of in-plane XRD peaks obtained from strained-Si layers is much larger than for un-strained SOI and bulk Si, reflecting poor crystal quality. SSOI was fabricated by the layer transfer of strained-Si on a virtual SiGe substrate. Therefore, we believe the crystal quality and strain distribution originate in the donor strained Si when virtual SiGe substrate is the starting material.     

Improved operability in Hg1−xCdxTe detector arrays

As liquid phase epitaxial (LPE) growth and array fabrication processes have matured to give excellent wafer average performance, the yield limiter for infrared focal plane arrays (IRFPAs), especially large ones, have become outages. In this work, significant progress has been made in identifying the source and eliminating outages from LPE grown Hg_1−xCd_xTe P-on-n structures. Historically, studies of the sources of outages have employed defect etches to look for dislocations and other crystalline defects, and secondary ion mass spectroscopy (SIMS), imaging SIMS, and sputter initiated resonance ion spectrometry (SIRIS) to look for impurities at critical interfaces. Using these techniques, trends were established, but direct correlation with outages have been observed. In LPE grown materials, where the dislocation densities are always below 5×10⁵ cm⁻², and often below 1×10⁵ cm⁻² on CdZnTe substrates, dislocations only account for a few outages. In order to understand the source(s) of outages, a failure analysis was performed on several long wavelength IRFPAs. Using a dilute etchant, the metals and then cap layers of some 64×64 pixel IRFPAs which had excellent average performance, but suffered from a high density of pixels with excessive leakage current, were removed. Using a scanning electron microscope with energy dispersive spectroscopy capability, the presence of carbon particles was correlated with excessive leakage current on a 1:1 pixel basis. A series of experiments was then conducted which isolated the source of the particles to the cap layer growth process, which was consequently changed to eliminate them. The process improvements have reduced the particle density to below the measurement limit of the optical measurement technique implemented to monitor the density of particles on witness wafers. These improvements are resulting in IRFPAs with significantly improved operability.     

The isolation and nucleation of misfit dislocations in strained epitaxial layers grown on patterned,ion-damaged GaAs

As shown previously, the misfit dislocation density of strained epitaxial III–V layers can be significantly reduced by isolating sections (via patterned etching) of a GaAs substrate before epitaxial growth. A disadvantage of this technique is that the wafer surface is no longer planar, which can complicate subsequent device fabrication. As an alternative, we have investigated growth of 350 nm of In_0.5Ga{0.95}As by molecular beam epitaxy at two temperatures on substrates which were patterned and selectively damaged by Xe ion implantation (300 keV, 10¹⁵ cm²). Selectively etched substrates were prepared as reference samples as well. The propagation of the misfit dislocations was stopped by the ion-implanted regions of the low growth temperature (400° C) material, but the damaged portions also acted as copious nucleation sources. The resulting dislocation structure was highly anisotropic, with dislocation lines occurring in virtually only one direction. At the higher growth temperature (500° C) the defect density fell, but the ion damaged sections no longer blocked dislocation glide. Images from cathodoluminescence and transmission electron microscopy show thatthe low growth temperature material has a dislocation density of 70,000 cm^-1 in the 110 direction and less than 10,000 cm^-1 in the 110 direction. Ion channeling and x-ray diffraction show that strain is relieved in only one direction. The strain relief is consistent with the relief derived from TEM dislocation counts and Burgers vector determination. However, even this high dislocation count is not sufficient to reach the expected equilibrium strain. Reasons for the anisotropy are discussed.     

Probing into Reverse Bias Dark Current in Perovskite Photodiodes: Critical Role of Surface Defects

Minimizing reverse bias dark current density (J_dark) while retaining high external quantum efficiency is crucial for promising applications of perovskite photodiodes, and it remains challenging to elucidate the ultimate origin of J_dark. It is demonstrated in this study that the surface defects induced by iodine vacancies are the main cause of J_dark in perovskite photodiodes. In a targeted way, the surface defects are thoroughly passivated through a simple treatment with butylamine hydroiodide to form ultrathin 2D perovskite on its 3D bulk. In the passivated perovskite photodiodes, J_dark as low as 3.78 × 10^-10 A cm^-2 at -0.1 V is achieved, and the photoresponse is also enhanced, especially at low light intensities. A combination of the two improvements realizes high specific detectivity up to 1.46 × 10¹² Jones in the devices. It is clarified that the trap states induced by the surface defects can not only raise the generation-recombination current density associated with the Shockley–Read–Hall mechanisms in the dark (increasing J_dark), but also provide additional carrier recombination paths under light illumination (decreasing photocurrent). The critical role of surface defects on J_dark of perovskite photodiodes suggests that making trap-free perovskite thin films, for example, by fine preparation and/or surface engineering, is a top priority for high-performance perovskite photodiodes.     

Investigation of microstructure and V-defect formation in In<Subscript>x</Subscript>Ga<Subscript>1−x</Subscript>N/GaN MQW grown using temperature-gradient metalorganic chemical vapor deposition

Temperature-gradient metalorganic chemical vapor deposition (MOCVD) was used to deposit In_xGa_1−xN/GaN multiple quantum well (MQW) structures with a concentration gradient of indium across the wafer. These MQW structures were deposited on low defect density (2×10⁸ cm⁻²) GaN template layers for investigation of microstructural properties and V-defect (pinhole) formation. Room temperature (RT) photoluminescence (PL) and photomodulated transmission (PT) were used for optical characterization, which show a systematic decrease in emission energy for a decrease in growth temperature. Triple-axis x-ray diffraction (XRD), scanning electron microscopy, and cross-sectional transmission electron microscopy were used to obtain microstructural properties of different regions across the wafer. Results show that there is a decrease in crystal quality and an increase in V-defect formation with increasing indium concentration. A direct correlation was found between V-defect density and growth temperature due to increased strain and indium segregation for increasing indium concentration.     

Radiation-thermal activation of silicon implanted in gallium arsenide

The layer density, density profile, and mobility of electrons in ²⁸Si-ion-doped layers of semiinsulating GaAs after radiation annealing with electron energy above and below the defect formation threshold and after thermal annealing in the temperature range T _a =590–830 °C are investigated. It is shown that for radiation annealing energy above the defect formation threshold ion-doped layers are formed with much lower annealing temperatures, and the degree of electrical activation of silicon in these layers is high and the density of electron mobility limiting defects is low. Fiz. Tekh. Poluprovodn. 33, 687–690 (June 1999)     

IntegratedIn Situ wafer and system monitoring for the growth of CdTe/ZnTe/GaAs/Si for mercury cadmium telluride epitaxy

Reproducible improvements in the metalorganic vapor phase epitaxy (MOVPE) grown CdTe buffer quality have been demonstrated in a horizontal rectangular duct silica reactor by the use of integratedin situ monitoring that includes laser reflectometry, pyrometry, and Epison concentration monitoring. Specular He-Ne laser reflectance was used toin situ monitor the growth rates, layer thickness, and morphology for both ZnTe and CdTe. The substrate surface temperature was monitored using a pyrometer which was sensitive to the 2–2.6 μm waveband and accurate to ±1°C. The group II and group VI precursor concentrations entering the reactor cell were measured simultaneously using two Epison ultrasonic monitors and significant variations were observed with time, in particular for DIPTe. The surface morphology and growth rates were studied as a function of VI/II ratio for temperatures between 380 and 460°C. The background morphology was the smoothest for VI/IIratio in the vicinity of 1.5–1.75 and could be maintained using Epison monitors. Regularly shaped morphological defects were found to be associated with morphological defects in the GaAs/Si substrate. The x-ray rocking curve widths for CuK_α (531) reflections were in the range of 2.3–3.6 arc-min, with no clear trend with changing VI/II ratio. X-ray topography images of CdTe buffer layers on GaAs/Si showed a mosaic structure that is similar to CdTe/sapphire substrates. The etch pit density in Hg_1-xCd_xTe layers grown onto improved buffer layers was as low as 6 x 10⁶ cm^-2 for low temperature MOVPE growth using the interdiffused multilayer process.     

Comparative Studies of Carrier Dynamics in 3C-SiC Layers Grown on Si and 4H-SiC Substrates

Time-resolved nonlinear optical techniques were applied to determine the electronic parameters of cubic silicon carbide layers. Carrier lifetime, τ, and mobility, μ, were measured in a free-standing wafer grown on undulant Si and an epitaxial layer grown by hot-wall chemical vapor deposition (CVD) on a nominally on-axis 4H-SiC substrate. Nonequilibrium carrier dynamics was monitored in the 80 K to 800 K range by using a picosecond free carrier grating and free carrier absorption techniques. Correlation of τ(T) and μ _a(T) dependencies was explained by the strong contribution of diffusion-limited recombination on extended defects in the layers. A lower defect density in the epitaxial layer on 4H-SiC was confirmed by a carrier lifetime of 100 ns, being ~4 times longer than that in free-standing 3C.     

Photothermal Activation of Shallow Dopants Implanted in Silicon

Dopant impurities were implanted at high dose and low energy (10¹⁵ cm⁻², 0.5–2.2 keV) into double-side polished 200 mm diameter silicon wafers and electrically activated to form p–n junctions by 10 s anneals at temperatures of 1,025, 1,050, and 1,075°C by optical heating with tungsten incandescent lamps. Activation was studied for P, As, B, and BF₂ species implanted on one wafer side and for P and BF₂ implanted on both sides of the wafer. Measurements included electrical sheet resistance (Rs) and oxide film thickness. A heavily boron-doped wafer, which is optically opaque, was used as a hot shield to prevent direct exposure to lamp radiation on the adjacent side of the test wafer. Two wafers with opposing orientations with respect to the shield wafer were annealed for comparison of exposure to, or shielding from, direct lamp illumination. Differences in sheet resistance for the two wafer orientations ranged from 4% to 60%. n-Type dopants implanted in p-type wafers yielded higher Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been reduced. p-Type dopants implanted in n-type wafers yielded lower Rs when the implanted surface was exposed to the lamps, as though the effective temperature had been increased. Effective temperature differences larger than 5°C, which were observed for the P, B, and BF₂ implants, exceeded experimental uncertainty in temperature control.