Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi‐standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual‐clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi‐operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance‐area trade‐off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.     

A 1-V, 1.2-mA fully integrated SoC for digital hearing aids

Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for today׳s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130 nm CMOS technology. The measurement results show that the analog front-end has up to 88 dB signal-to-noise ratio. And the DSP platform consumes about 0.86 mA current at 8 MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2 mA at 1 V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers.     

CORDIC based fast algorithm for power-of-two point DCT and its efficient VLSI implementation

—In this paper, we present a coordinate rotation digital computer (CORDIC) based fast algorithm for power-of-two point DCT, and develop its corresponding efficient VLSI implementation. The proposed algorithm has some distinguish advantages, such as regular Cooley-Tukey FFT-like data flow, identical post-scaling factor, and arithmetic-sequence rotation angles. By using the trigonometric formula, the number of the CORDIC types is reduced dramatically. This leads to an efficient method for overcoming the problem that lack synchronization among the various rotation angles CORDICs. By fully reusing the uniform processing cell (PE), for 8-point DCT, only four carry save adders (CSAs)-based PEs with two different types are required. Compared with other known architectures, the proposed 8-point DCT architecture has higher modularity, lower hardware complexity, higher throughput and better synchronization.     

Domain Specific Tools and Methods for Application in Security Processor Design

Security processors are used to implement cryptographic algorithmswith high throughput and/or low energy consumption constraints. The designof these processors is a balancing act between flexibility and energy consumption.The target is to create a processor with just enough programmability to covera set of algorithms—an application domain. This paper proposes GEZEL,a design environment consisting of a design language and an implementationmethodology that can be used for such domain specific processors. We use thesecurity domain as driver, and discuss the impact of the domain on the targetarchitecture. We also present a methodology to create, refine and verify asecurity processor.     

A disciplined approach to the development of platform architectures

Silicon capability has enabled the embedding of an entire system on a single silicon die. These devices are known as systems-on-a-chip. Currently, the design of these devices is undisciplined, expensive, and risky. One way of amortizing the cost and ameliorating this design risk is to make a single integrated circuit serve multiple applications, and the natural way of enabling this is through end-user programmability. The aim of the MESCAL project, which is the subject of this paper, is to introduce a disciplined approach to producing reusable architectural platforms that can be easily programmed to meet a variety of applications. (MESCAL stands for Modern Embedded Systems, Compilers, Architectures, and Languages.)     

一种超小型AES专用处理器的FPGA实现

提出一种基于FPGA的专用处理器设计.它是用于高级加密标准的超小面积设计,支持密钥扩展(现在设计为128位密钥),加密和解密.这个设计采用了完全的8位数据路径宽度,创新的字节替换电路和乘累加器结构,在最小规模的Xilinx Spartan II FPGA芯片XC2S15上实现了一个高级加密标准AES的专用处理器,使用了不到60%的资源.当时钟为70MHz时,可以达到平均加密解密吞吐量2.1Mb/s.主要应用在把低资源占用,低功耗作优先考虑的场合.     

一种用于数字助听器的次毫瓦级语音处理平台

We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit applicationspecific instruction-set processor （ASIP） and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP＇s instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.     

网络处理器的分析与演进

文章从网络处理器的出现首先分析了网络处理器具备的基本功能特性,接着介绍了网络处理器体系结构的演进过程,在文章的最后部分对当前市场上的主流产品作了一个大概的介绍,并对网络处理器今后的发展作了简单的描述.     

高性能PLC专用指令集处理器设计与仿真

该高性能PLC专用指令集处理器采用自主设计的PLC专用指令集,符合PLC指令特征,可减少该PLC专用指令集处理器执行的指令数,并采用32位RISC体系结构加快PLC程序的执行速度.该高性能PLC专用指令集处理器采用哈佛总线结构,寄存器组采用位编址模式,位处理器可加速PLC布尔运算,功能块单元可提高功能块指令执行的精度,并采用四级流水线提高PLC指令的执行速度.现已完成了该高性能PLC专用指令集处理器的系统功能仿真,经测试仿真结果正确.     

低功耗肖特基TTL300门阵列电路

本文对ST300门阵列电路作了简要介绍,描述了单元电路和I/O驱动电路的电路设计、版图设计和版图结构以及人工布线与计算机辅助设计制版系统相结合的布线技术。     

面向密码流体系结构的超长指令字可重构研究

可重构密码流体系结构是一种面向密码运算的新型体系结构,但存在着超长指令字(VLIW)代码稀疏和Kernel体积过大的问题。该文以可重构密码流处理架构S-RCCPA为研究平台,通过大量密码算法在S-RCCPA架构上的适配分析,提出了VLIW可重构技术,并设计了Kernel级指令集、VLIW可重构算法及指令可重构单元。实验证明,该技术能够有效提高VLIW的指令密度,同时降低了VLIW的指令宽度,使得整个Kernel体积减小了约33.3%,并将微码存储器的容量由96 kB降为64 kB,有效降低芯片整体面积和系统功耗。     

基于基金会现场总线协议的接口芯片设计

介绍了一个基于基金会现场总线协议的专用接口芯片设计。该芯片（HKFF）依据IEC61158标准的物理层及数据链路层规范设计,实现接收和发送31．25kbit／s的数据处理,帧同步,自动地址匹配,帧检测序列产生／校验。曼彻斯特编解码等功能。为便于软件的操作,该芯片含有若干特殊寄存器。HKFF芯片设计完成后,采用TSMC0．25微米工艺一次流片成功。     

基于GF(2~n)的ECC协处理器芯片设计

文章讨论了定义在GaloisField(GF)2有限域上椭圆曲线密码体制(ECC)协处理器芯片的设计。首先在详细分析基于GF(2n)ECC算法的基础上提取了最基本和关键的运算,并提出了通过协处理器来完成关键运算步骤,主处理器完成其它运算的ECC加/解密实现方案。其次,进行了加密协处理器体系结构设计,在综合考虑面积、速度、功耗的基础上选择了全串行方案来实现GF(2n)域上的乘和加运算。然后,讨论了加密协处理器芯片的电路设计和仿真、验证问题。最后讨论了芯片的物理设计并给出了样片的测试结果。     

专用指令集处理器系统级设计方法

以专用指令集处理器（ASIP）为核心的SoC系统是基于特定应用,设计嵌入式处理器的一个重要发展方向。给出了一种高效的系统级指令集模型设计空间搜索和体系结构仿真的方法。该方法可以在设计的早期阶段对软件和硬件进行协同设计和仿真,针对应用优化系统性能。利用该方法成功设计的ASIP系统,完成基4-64点DIF FFT需要310个时钟周期。     

一种电机FOC算法DSP系统设计及实现

本文设计了一种适用于电机矢量控制算法的数字信号处理系统的微架构定义,包括其指令集定义、存储器模型以及与主CPU的交互模式.该设计具有通过固定部分多操作数有效缩减指令编码长度提高代码密度以及后台执行多周期指令提高ALU并行效率的显著优点.文中给出了典型的FOC控制算法在DSP （Digital Signal Processor）指令集上实现的指令周期数,也给出了对应架构的电路实现情况,最终以ARM CORTEX-M0及几款主流DSP作为比较基线,通过实测实验数据证明了体系结构的高能效比,以较为有限的电路面积代价,极大提高了集成DSP的嵌入式系统的运行效率.     

An advanced finite element strategy for thermal stress field investigation in aluminium interconnections during processing of very large scale integration multilevel structures

An advanced strategy for modelling the thermal stress induced in aluminium interconnections during processing of multilevel structures is presented. The advantage of the approach described is that it allows the residual stresses from one processing step to be used as the initial conditions for a subsequent step. 2D elasto-plastic model (von Mises plastic criterion) is implemented in Finite Element Code and it is shown that even after significant relaxation by plastic deformation, high thermal stress resides in the aluminium line in both width and thickness directions. The technique demonstrated here is for a silicon-glass–aluminium-glass structure. However, it is readily extended to more complex situations and material combinations.     

BiCMOS技术在通信领域的研究与进展

为了促进我国通信用高性能电子电路和各种通信ASIC新产品的设计、研制和应用,本文首先论述了性能卓越的BiCMOS技术的先进性,然后讨论了国外流行的两种BiCMOS工艺制作技术及其特殊考虑,以及在通信工程中的应用电路,最后分析了BiCMOS技术在我国高速通信、信息处理电路和系统(如CPU、SRAM、DSP、SOC和数/模混合电路等)中的应用前景和发展趋势。文中提出了运用先进的BiCMOS技术于中国通信电路和系统中的观点。     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.