共查询到20条相似文献,搜索用时 15 毫秒
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The dynamic reconfiguration technique based on field-programmable gate array (FPGA) can improve the resource utilization.Discussed are the dynamic reconfiguration principles and methods.Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet Physical layer transceiver(PHY).The hardware of the system is designed with Xilinx Virtex-II XC2V30P FPGA that embedds MicroBlaze and MAC IP core,and its network communication software based on transmission control protocol/Internet protocol (TCP/IP) protocol is programmed by loading LwlP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system(RFDRS) can switch freely in the eight lighting modes of light emitting diodes (LED),and that,using dynamic reconfiguration technology,FPGA resource utilization can be reduced remarkably,which is advantageous in the system upgrade and software update. 相似文献
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Application of Global Dynamic Reconfiguration in Artificial Neural Network System based on Field Programmable Gate Array 总被引:1,自引:1,他引:0
Presented is a global dynamic reconfiguration design of an artificial neural network based on field programmable gate array (FPGA). Discussed are the dynamic reconfiguration principles and methods. Proposed is a global dynamic reconfiguration scheme using Xilinx FPGA and platform flash. Using the revision capabilities of Xilinx XCF32P platform flash, an artificial neural network based on Xilinx XC2V30P Virtex-Ⅱ can be reconfigured dynamically from back propagation (BP) learning algorithms to BP network testing algorithms. The experimental results indicate that the scheme is feasible, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably. 相似文献
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针对当前图像处理系统存在的处理性能和系统灵活性等问题,提出了一种采用可重构技术和图像并行处理技术实现的图像处理系统。研究了动态可重构技术理论及可重构系统的特点,并且研究了图像并行处理系统的设计及算法实现的方法,分析了目前图像处理系统中存在的问题,利用FPGA(Field)可以多次重复配置的特性,设计了可重构图像并行处理系统。同时,在研究了分布式算法的基础上,实现了图像处理算法。设计了采用多IP核实现图像并行处理系统。系统可以根据计算任务的不同,并同时考虑到并行处理系统负载平衡性,设置不同的计算节点数量,达到了既能够满足系统的需求,又可以节约硬件成本的效果。通过实验,验证了系统的可行性。 相似文献
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针对目前FPGA的动态配置和加载方法存在的速率低,在电磁环境恶劣的情况下加载不稳定的问题,在典型配置方法的基础上提出了一种利用于FPGA内部专用加载逻辑,采用状态机控制的新型的FPGA快速动态配置和远程加载的方法,详细介绍了该方法的硬件架构设计,动态配置软件设计和远程加载软件设计,实验证明该方法实现简单,稳定可靠、抗干扰能力强。 相似文献
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随着FPGA的广泛应用,其实现的功能也越来越多,FPGA的动态重构设计就显得愈发重要。在分析Xilinx VertexⅡPro系列FPGA配置流程、时序要求的基础上,设计了基于CPLD的FPGA快速动态重构方案,实现了同一硬件平台下多个FPGA设计版本的在线动态配置和功能重构,该技术已在工程中成功应用。 相似文献
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在动态局部可重构设计过程中,系统级设计到现场可编程门阵列(FPGA)硬件实现,还需要大量的寄存器传输级(RTL)硬件语言编写,导致设计效率下降的问题。针对该问题,以Xilinx公司最新提出的动态局部重构设计流程———早期获取部分可重构(EAPR)为基础,利用System Generator软件,提出一种动态局部重构的设... 相似文献
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在分析传统FPGA动态重构方法性能缺陷的基础上,创新性的提出了基于改进型游程编码的FPGA动态重构方法,并详细介绍了该方法的设计实现。与传统FPGA动态重构方法对比测试结果表明,基于改进型游程编码的FPGA动态重构方法不仅可以显著提高FPGA动态重构的速度,而且可以降低对程序存储器容量要求。目前,该技术已在重大工程项目中得到应用。 相似文献
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随着国产化航空管制雷达的推进,设计了一种高可靠性的通用点迹处理硬件平台,其具有多种形式的高速接口和强大的处理能力,为航迹和点迹交互、雷达点迹处理的双套冗硬件提供了一种可能。该平台以DSP+FPGA为主要处理器件,可同时处理4个通道雷达点迹数据,在接口上以标准CPCI总线和6对传输速率可达5 Gbit·s-1的高速通道为主要通信接口,可满足多通道间的数据交换。以某种类型的双套冗余雷达为例,点迹处理算法在该平台上的工程实现表明,算法对于点迹处理和点航迹交互以及帧间点迹滤波在工程实现上具有较好的应用价值。 相似文献
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FPGA的全局动态可重配置技术主要是指对运行中的FPGA器件的全部逻辑资源实现在系统的功能变换,从而实现硬件的时分复用。提出了一种基于systemACE的全局动态可重配置设计方法,首先介绍Xilinx SystemACE技术,详细分析FPGA的全局动态可重配置的原理,使用SystemACE控制器件和Compact Flash卡,并讨论了其中的若干细节,然后基于SystemACE实现了Virtex一5系列FPGA全局动态可重配置。实验结果表明,该方法稳定可靠,可实现8种不同比特流的动态配置,与传统的FPGA配置方法相比,其配置更灵活。 相似文献
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The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption. 相似文献
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A method for the fabrication of a biomimetic Janus composite membrane is reported here. This approach is based on a membrane with a vertical gradient crosslinking degree, which is achieved through UV light–induced dimerization of anthracene grafted on poly(styrene‐block‐butadiene‐block‐styrene) chains in the presence of carbon nanotubes. UV light penetration is controlled by the accretion of carbon nanotubes to ultimately tailor the heterogeneous crosslinking degree in thickness. This kind of Janus structure is applied here for shape actuation. Here, solvent or shape memory effect–induced shape morphing is obtained via the heterogeneous swelling (deswelling) abilities of, or internal stress from, the Janus structure. By tailoring the UV light irradiation time, the irradiated region and the prestrain, sophisticated and multiple types of shape morphing are programed. In addition, this type of Janus structure can shift back to the homogeneous structure via dedimerization of the anthracene dimers upon thermal treatment, which provides extensive freedom for the design of smart responsive actuators. 相似文献
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介绍Gbps无线通信试验系统中高速串行数据接口的设计与实现。按照Gbps无线通信试验系统对高速串行数据的传输要求,数据传输速率超过1 Gb/s,在基于Xilinx IP core技术上对单板上的FPGA进行逻辑设计,实现了符合系统要求的高速串行数据接口。在系统实际调试中,通过ATCA机箱背板进行数据传输,获得了高达Gbps的数据吞吐速率且传输误码率低于10-14。 相似文献
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为实现激光目标回波的快速捕获、检测及实时处理,提出一种ADC FPGA DSP的数据采集与实时处理的设计.激光回波通过高速模数转换器(ADC)转换成数字信号,经FIFO乒乓高速缓存,然后再送到DSP进行实时处理.电路简单、可靠、实时性强,最高采样率达200 MHz,具有8 bit垂直分辨率,4 M×8位数据存储空间.该系统能准确实时地计算出目标距离、速度,适时预警,符合汽车防撞激光雷达中信号处理的要求.详细介绍了系统的设计方案及各主要组成模块. 相似文献