A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I _s , threshold voltage V _T0, gamma γ, θ _o (dependent on mobility degradation and source-drain series resistances), and θ _e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23–61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

An experimental and theoretical analysis of double-diffused MOS transistors

An experimental and theoretical study of double-diffused MOS transistors (DMOST's) has been made. A simple, analytic two-transistor model gives insight into DMOS device physics as well as predicting DMOST characteristics. Both the model and experimental results show that three distinct regions of operation exist: short-channel control, long-channel control, and carrier velocity saturation control. Quantitative criteria are established for judging the region of operation as a function of device parameters and terminal voltages. A DMOST may be optimized to have the same d.c. characteristics as its short-channel component transistor over most of its operating range. A two-transistor model suitable for Computer-Aided Circuit Design (CAD) is also presented.     

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.     

A novel technique to determine the gate and drain bias dependentseries resistance in drain engineered MOSFETs using one single device

A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived     

High-accuracy physical modeling of submicrometer MOSFET's

When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.     

Minority carrier injection characteristics of the diffused emitter junction

For the double-diffused transistor, a one-dimensional analysis is presented on the minority carrier injection properties of a diffused emitter junction. This junction is bounded on one side by a reverse biased collector and on the other by an ohmic contact of arbitrary recombination velocity. Furthermore, arbitrary magnitudes of minority carrier lifetime are assumed in both the emitter and base regions of this semiconductor device. Injection efficiency characteristics are graphically illustrated throughout a wide range of physical and geometrical parameters. Assuming, for example, variations in the emitter junction depth, injection properties are demonstrated for transistors exhibiting a fixed collector location and also for transistors exhibiting a fixed base width. A comparison is also shown between the calculated minority carrier injection from this analysis and from other, more approximate, methods.     

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.     

Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

Temporal noise such as thermal and low-frequency noise (LF noise) in the CMOS imager readout circuit has been analyzed. In addition, the effect of correlated double sampling operation on the noise was included. We have derived an analytical noise equation for the specified readout circuit, and confirmed its validity by comparing it with the simulation result. Thermal noise model which is accurate in short-channel devices operating in saturation region was used. Since the in-pixel devices (source follower and selection transistor) of the readout circuit are relatively small in size, and thus exhibits random telegraph signal (RTS) noise, both 1/f and RTS noise were considered for their LF noise. Based on the analyzed noise components, we presented the noise reduction method by adjusting the transistors sizes in the readout circuit.     

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.     

Engineering model of MOS transistors for the 60-300 K temperature range

The authors present the first engineering model of short-channel MOS transistors that is applicable to cryogenic CMOS. The new model incorporates the nonuniversal dependence of the effective channel mobility on the effective vertical field which is ignored in the room temperature device models. The proposed model is verified by comparison with experimental device characteristics obtained over a wide range of temperatures and channel lengths.<>     

Subthreshold conduction in silicon-on-sapphire transistors

The subthreshold conduction in silicon-on-sapphire MOS transistors has been studied both theoretically and experimentally. A simple model to describe the subthreshold conduction current for both thick films and thin films is derived in terms of charges in the silicon and charges at the silicon-silicon dioxide and silicon-sapphire interfaces. The model has been extended to cover short-channel transistors by application of charge conservation under the channel region. It is shown that the subthreshold conduction current for a SOS-MOS transistor has a form similar to that found in bulk transistors, but with modification of the terms due to the finite silicon film thickness and the unique geometry of the SOS-MOS transistor. The general form of the model has been confirmed by measurement of the subthreshold current on several hundred SOS-MOS transistors of different geometries manufactured by various companies.     

A closed-form delay expression for digital BiCMOS circuits withhigh-injection effects

A non-iterative formula is derived for calculating the delay time of digital BICMOS circuits with their bipolar transistors operating in high-current regime. Effects such as the base transit-time increase of minority carriers and the decrease of the current gain of the bipolar transistors are all incorporated in the model. This model can be used to investigate the effects of most device parameters such as transistor sizes and external loading on the performance of the circuits without resorting to any iterative procedures. This simplified model compares well with the original model to 10% over a wide range of operating conditions, and is especially accurate for situations where base widening affects the bipolar transistors     

A SPICE compatible subcircuit model for lateral bipolar transistorsin a CMOS process

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 μm CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJT's)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction     

Electrical characterization of feature sizes and parasitic capacitances using a single test structure

Commonly, transistor characteristics, feature sizes, and interfaces as well as oxide quality of MOS transistors are measured on different test patterns. For short-channel devices this can lead to wrong interpretations because the various parameters strongly depend on each other. The present paper describes capacitance measurements which allow the determination of relevant parameters by using only a single multitransistor test structure. The method is very accurate and simple and can be used for device and process characterization.     

Direct writing of inkjet-printed short channel organic thin film transistors

A direct-writing fabrication process for fully inkjet-printed short-channel organic thin-film transistors (OTFTs) has been developed. Channels as narrow as 800 nm between two printed Ag electrodes were achieved by printing a special Ag ink on an SU-8 interlayer, which can be partially dissolved by the solvents used in the Ag ink. The ridge formed along the printed Ag line edges due to redistribution of the interlayer material during the drying process limits the ink spread, and separates neighboring printed lines, and is the key to defining an ultra-narrow channel for transistor fabrication. The short-channel OTFTs fabricated using this technique have demonstrated well-defined linear and saturation regimes. An extracted mobility of 0.27 cm²/Vs with an on/off ratio of 10⁵ was obtained at a driving voltage of −12 V. The excellent performance of these devices demonstrates the potential of this technique in fabrication of short-channel devices using standard printing technologies.     

Transistor operation of 30-nm gate-length EJ-MOSFETs

We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFET's) to investigate transistor characteristics of ultrafine-gate MOSFET's. By using EB direct writing onto an ultrahigh-resolution negative resist (calixarene), we achieved a gate length of 32 nm for the first time. The short-channel effects were effectively suppressed by electrically induced ultrashallow source/drain regions, and the fabricated device exhibited normal transistor characteristics even in the 32-nm gate-length regime at room temperature: an ON/OFF current ratio of 10 ⁵ and a cut-off current of 20 pA/μm     

A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits

Edge contact transistors are widely used in basic cells of gate-array circuits and custom designed circuits. The role of sheet and contact in affecting the performance of these transistors is investigated. A two-dimensional model has been developed to calculate the transistor's effective series resistance at various bias conditions. Very good correlation between the model and experiments has been obtained. It is found that different series resistances are observed in linear and saturation regions for edge contacts transistors in contrast to the conventional transistors. The results show that the effective series resistance of an edge contact transistor is nonuniform and is a complex function of the gate voltage, the drain voltage, and the linear or saturation bias conditions.     

Mismatch reduction technique for transistors with minimum channel length

An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and −3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier’s anticipated input-referred offset voltage improves to 0.76–1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6–1.0%.     

Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images

Short-channel MOS transistordV_{T}/dV_{DS}characteristics are expressed by an analytic function of fundamental device parameters. The expression is derived from a simple model of short-channel MOS transistors in threshold condition, which is based on a point charge and its mirror images. With this expression,dV_{T}/dV_{DS}is found to be proportional to1/L^{2}-1/L^{4}, whereLis channel length. Following factors are also found, wherein the source and drain junction depth effect is only logarithmic ondV_{T}/dV_{DS}characteristics,dV_{T}/dV_{SUB}anddV_{T}/dV_{DS}are closely related in short-channel MOS transistors, and short-channel effects are expected to be smaller in MOS transistors on SOS than on bulk silicon, due to a large number of Si/sapphire interface states. This model is simple, and it can be applied to short-channel MOS transistor designing and circuit simulations.