一种分片式多核处理器的用户级模拟器

随着片上晶体管资源的增多和互连线延迟的加大,分片式多核微处理器已成为多核处理器设计的新方向.为了对这种新型处理器进行体系结构的深入研究和设计空间的探索,设计并实现了针对分片式多核处理器的用户级多核性能模拟器.该多核模拟器在龙芯2号单处理器核的基础上,完整地模拟了基于目录的Cache一致性协议和存储转发式片上互联网络的结构模型,详细地刻画了由于系统乱序处理各种请求应答和请求之间的冲突而造成的时序特性,可以通过运行各种串行或并行的工作负载对多核处理器的各种重要性能指标加以评估,为多核处理器的结构设计提供了快速、灵活、高效的研究平台.     

SimTile:片状多核处理器的高效模拟器(英文)

传统的基于共享总线的多核芯片随着核心数增加产生了瓶颈问题。新型TiledCMP(chip multiprocessor)的结构设计中,片上核心互联网络对提高扩展能力和执行效率起到了重要作用。为了实现低延迟、高带宽的核心通信,高速点对点网络方式的片上多核互联结构模拟成为研究的热点。抽象片上Tiled方式16核功能单元结构,设计实现了SimTile模拟器,可提供配置灵活、功能单元齐全的片上多核处理器设计,支持高效率的全局共享缓存、高速片上路由结构。模拟器采用模块化的组件配置方式,片上核心数量与互联网络结构、数据一致性协议、全局寄存器通信与cache共享模式等,均可通过精简的参数调整。实验表明模拟器执行效率较高,为片上多核研究提供了灵活、高效并具备可扩展性的新平台。     

OpenCMP：一个支持事务存储模型的多核处理器模拟器

CPU设计正在由仅开发指令级并行性的单线程单核结构转向利用线程级并行性的多线程多核结构，但至今还没有一个可移植性好并被广泛使用的开源多核处理器模拟器，限制了在这样的结构上开展高质量的研究工作。我们开发了一个多核处理器体系结构模拟器OpenCMP，用于支持当前和未来对多线程多核处理器体系结构关键技术的研究。该模拟器适当地抽象了多核处理器结构，为主流的多核处理器结构研究提供一个可扩展、灵活的模拟工具框架，包括支持对乱序、顺序的处理器核和同时多线程处理器核的模拟，以便对更大的多核设计空间进行比较性研究。本文以支持事务存储模型的多核处理器结构模拟器为例，详细描述了如何通过抽象多核结构和事务存储模型的最基本特性和组成部分，扩展单核处理器模拟器SimpleScalar，设计与实现一个多核处理器模拟器。初步研究表明，与现有的多核处理器模拟器相比，该模拟器能够较好地支持对事务存储模型和基于事务存储模型的多核处理器体系结构的研究．     

同构与异构片上多核系统的演进过程

系统级芯片是高端电子系统的核心,而片上多核系统是近年来系统级芯片的主要实现形式。近十年来,片上多核系统一直是数字集成电路领域的热点,经过众多研究者的不断努力诞生了大量很有意义的研究成果。但由于片上多核系统的研究者背景和应用领域不同导致发展演进过程较为复杂而难以理解。为减少这一问题的影响,总结了片上多核系统的演进历史与现状,并对片上多核系统未来的发展提出了一些看法。     

支持存储访问的NoC模拟器的设计与实现

随着片上网络的发展,片上多处理器系统通信性能提高的同时,存储器的访问性能将成为片上多处理器系统的性能瓶颈.目前片上网络的研究主要依赖于模拟器,而现有的片上网络模拟器都不能完成对存储器访问的准确模拟.本文设计并实现了一个能对存储器访问进行模拟的模拟器,为存储器性能的研究提供了一个实验平台;论文通过采用大量访问集对该模拟器进行测试,得出了若干条与存储器访问性能优化相关的片上网络设计建议.     

异步片上网络研究综述

异步片上网络具有低动态功耗、对延迟抖动的不敏感、统一的网络接口、较低的系统集成复杂度和较好的电磁兼容能力等众多特性,是下一代片上多核微处理器和多核片上系统的标准片上通信架构之一.在简单介绍异步电路的相关理论后,从多个方面概述了当前异步片上网络的研究成果,包括网络拓扑、同步?异步接口、流控制、服务质量、路由算法、低功耗设计、容错和可测性设计以及设计自动化;然后介绍并分析了一些具有代表性的异步片上网络设计案例.研究显示,异步片上网络具有众多同步片上网络所不具备的优点,大量的片上多核系统将使用异步片上网络作为其片上通信系统,但它们的易用性和网络性能亟待提高.     

基于2D Mesh拓扑结构的NoC模拟器设计

片上网络模拟器的设计涉及到片上网络的拓扑结构、路由器结构、路由算法、性能分析等诸多方面.从NoC模拟器设计的角度,研究并讨论模拟器所采用的拓扑结构,路由器结构及数据包格式,介绍拓扑结构模拟、IP核模拟、路由模拟,并且用面向对象语言C++实现一个NoC模拟器系统.     

ArmSim全系统模拟器的设计与实现

模拟器作为嵌入式系统研究的基础研发工具,可辅助系统体系结构调优、软硬件协同设计.本文实现了具有良好配置性及可扩展性的ArmSim模拟器,该模拟器是针对ARM处理器的全系统模拟器,可在其上运行和调试ARM应用级和系统级的目标程序.本文详细描述ArmSim的设计与实现细节.     

多核并行脉冲神经网络模拟器的设计

脉冲神经网络属于第三代人工神经网络,它是更具有生物可解释性的神经网络模型。随着人们对脉冲神经网络不断深入地研究,不仅神经元空间结构更为复杂,而且神经网络结构规模也随之增大。以串行计算的方式,难以在个人计算机上实现脉冲神经网络的模拟仿真。为此,设计了一个多核并行的脉冲神经网络模拟器,对神经元进行编码与映射,自定义路由表解决了多核间的网络通信,以时间驱动为策略,实现核与核间的动态同步,在模拟器上进行脉冲神经网络的并行计算。以Izhikevich脉冲神经元为模型,在模拟环境下进行仿真实验,结果表明多核并行计算相比传统的串行计算在效率方面约有两倍的提升,可为类似的脉冲神经网络的模拟并行化设计提供参考。     

可重定向的周期精确模拟器生成环境研究

针对嵌入式系统设计对模拟器生成环境可重定向性的要求,以及当今大多数生成环境多为功能级,而不支持周期级模拟的现状,本文提出了一个可重定向的周期精确模拟器的自动生成环境.通过体系结构描述语言xpADL对目标体系结构的组成和周期级行为进行描述,利用生成器和构件库完成了模拟器的生成.其中,xpADL的描述构架、生成器的分析机制和构件库中控制模拟框架的应用,使得与现有的生成环境相比,此环境在指令的周期级行为、流水线组织和流水化部件的模拟能力等方面均具有优势.实验部分完成了PISA和StrongARM两种体系结构的周期级模拟,并进行了针对加解密应用的流水线结构设计空间搜索的研究,证明了该环境的可重定向性和有效性.     

一种硬件事务存储系统模拟环境的研究与实现

针对事务存储技术研究中的模拟实验问题,实现了一种专门用于硬件事务存储系统的模拟环境,该模拟环境采用执行驱动模拟方式,支持全系统模拟,利用系统结构模拟器Simics和多核扩展包GEMS实现多核处理器相关部件的功能和性能模拟,在此基础上扩展实现硬件事务存储系统各部件的建模和模拟,以模块化的方法支持多种事务存储系统的模拟实验和性能评价.论文在分析事务存储和系统结构模拟技术的基础上,讨论了事务存储系统模拟环境的设计思路和方案,给出了该模拟环境的组成结构,并通过一种目标事务存储系统结构和一组测试程序对模拟环境进行了实验测试.     

LSE：一种处理器体系结构软件仿真器开发工具

在现代处理器体系结构设计中,利用软件仿真技术对设计结果进行验证是最重要的方面之一.然而,处理器体系结构仿真器的开发是一个非常困难的过程.主要的困难表现在三个方面:第一,目前用于处理器体系结构仿真器开发的编程语言如C或C 语言都是串行执行的语言,而处理器的各部件是可以并行运行的,使用串行编程语言编程来模拟并行执行的部件需要长时间的、仔细的程序功能与部件功能的匹配工作,并且容易出错;第二,使用串行程序来模拟并行部件的运行,模拟速度很低,并且仿真速度低是处理器体系结构软件仿真器开发领域的瓶颈问题;最后,仿真器仿真结果的可信度低也是一个关键问题.本文首先介绍了一种新的处理器体系结构软件仿真器开发工具,然后深入分析了该开发工具的优点和缺点,最后对该仿真器开发环境提出了改进方案.     

计算机体系结构软件模拟技术

在现代处理器或计算机系统设计中,体系结构软件模拟技术已成为一个不可缺少的环节.与不使用模拟技术的计算机系统或处理器设计方法相比,软件模拟技术可以极大地降低设计成本和缩短设计周期.然而,由于开发计算机体系结构软件模拟器通常十分困难,模拟器运行标准性能测试程序的时间很长以及模拟结果精度差等3个主要问题,限制了体系结构软件模拟技术在计算机系统设计中的有效性.许多研究人员已经提出了各种各样的方法和技术来解决这些问题,但是,到目前为止,这些问题还并未得到根本性解决.同时,未来体系结构模拟技术的新挑战已经开始显现.研究了体系结构软件模拟技术的由来和历史,对现有的技术和方法进行了分类和比较,对未来的挑战也进行了分析,指出了该领域今后的发展方向,以帮助计算机体系结构设计师或研究人员选择、开发体系结构模拟器或对该技术进行研究.基于这些调查分析,正在使用较为先进的技术开发一个适合于安腾系列架构的体系结构模拟器SimIPF.     

Performance issues in emerging homogeneous multi-core architectures

Multi-core architectures have emerged as the dominant architecture for both desktop and high-performance systems. Multi-core systems introduce many challenges that need to be addressed to achieve the best performance. Therefore, benchmarking of these processors is necessary to identify the possible performance issues. In this paper, broad range of homogeneous multi-core architectures are investigated in terms of essential performance metrics. To measure performance, we used micro-benchmarks from High-Performance Computing Challenge (HPCC), NAS Parallel Benchmarks (NPB), LMbench, and an FFT benchmark. Performance analysis is conducted on multi-core systems from UltraSPARC and x86 architectures; including systems based on Conroe, Kentsfield, Clovertown, Santa Rosa, Barcelona, Niagara, and Victoria Falls processors. Also, the effect of multi-core architectures in cluster performance is examined using a Clovertown based cluster. Finally, cache coherence overhead is analyzed using a full-system simulator. Experimental analysis and observations in this study provide for a better understanding of the emerging homogeneous multi-core systems.     

Cache-based high-level simulation of microthreaded many-core architectures

The accuracy of simulated cycles in high-level simulators is generally less than the accuracy in detailed simulators for a single-core systems, because high-level simulators simulate the behaviour of components rather than the components themselves as in detailed simulators. The simulation problem becomes more challenging when simulating many-core systems, where many cores are executing instructions concurrently. In these systems data may be accessed from multiple caches and the abstraction of the instruction execution has to consider the dynamic resource sharing on the whole chip. The problem becomes even more challenging in microthreaded many-core systems, because there may exist concurrent hardware threads. Which means that the latency of long latency operations can be tolerated from many cycles to just few cycles. We have previously presented a simulation technique to improve the accuracy in high-level simulation of microthreaded many-core systems, known as Signature-based high- level simulator, which adapts the throughput of the program based on the type of instructions, number of instructions and number of active threads in the pipeline. However, it disregards the access to different levels of the caches on the many-core system. Accessing L1-cache has far less latency than accessing off-chip memory and if the core is not able to tolerate latency, different levels of caches can not be treated equally. The distributed cache network along with the synchronization-aware coherency protocol in the Microgrid is a complicated memory architecture and it is difficult to simulate its behaviour at a high-level. In this article we present a high-level cache model, which aims to improve the accuracy in high-level simulators for general-purpose many-core systems by adding little complexity to the simulator and without affecting the simulation speed.     

SimK: A Large-Scale Parallel Simulation Engine

Simulation is an important method to evaluate future computer systems. Currently microprocessor architecture has switched to parallel, but almost all simulators remained at sequential stage, and the advantages brought by multi-core or many-core processors cannot be utilized. This paper presents a parallel simulator engine (SimK) towards the prevalent SMP/CMP platform, aiming at large-scale fine-grained computer system simulation. In this paper, highly efficient synchronization, communication and buffer management policies used in SimK are introduced, and a novel lock-free scheduling mechanism that avoids using any atomic instructions is presented. To deal with the load fluctuation at light load case, a cooperated dynamic task migration scheme is proposed. Based on SimK, we have developed large-scale parallel simulators HppSim and HppNetSim, which simulate a full supercomputer system and its interconnection network respectively. Results show that HppSim and HppNetSim both gain sound speedup with multiple processors, and the best normalized speedup reaches 14.95X on a two-way quad-core server.     

一种多核指令集仿真器构建技术

为了提高指令集仿真器的速度并降低多核构造的复杂度, 提出了一种多核指令集仿真器的快速搭建技术。该技术结合了解释型、编译型以及混合仿真策略的优点, 通过预解码技术、可扩展单核结构、单核结构中的cache和TLB模拟机制以及多核调度机制的相互配合, 以实现多核的快速搭建。该技术已经成功应用于基于中国科学院微电子所自主研发的IME-Diamond多核DSP的四核仿真器ISD的搭建。复杂度分析与实验结果表明, 该技术复杂度低且能够提高仿真速度。     

TMT: A TLB Tag Management Framework for Virtualized Platforms

Virtualization is a convenient way to efficiently utilize the numerous on-chip resources in modern physical platforms. However, it is important to ensure a high performance for the workloads running on such virtualized platforms. One factor which reduces the performance of these virtualized workloads is the frequent flushing of hardware-managed Translation Lookaside Buffers (TLBs). To avoid these flushes and reduce the TLB miss rate, we propose the Tag Manager Table (TMT), a hardware architecture for generating and managing process-specific TLB tags. Since the TMT approach is software-transparent, it is equally applicable for virtualized and non-virtualized environments. Using a full-system simulation approach, we investigate the reduction in the TLB miss rate achieved by using the TMT. We also analyze the variation of this reduction with factors like the size of the TMT, the TLB architecture and the workload characteristics and estimate the relative importance of these factors in determining this reduction.     

A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems

With Moore’s law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embedded systems exacerbates this design challenge and necessitates the architectural modeling of embedded systems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embedded systems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We verify our queueing theoretic modeling approach by running SPLASH-2 benchmarks on the SuperESCalar simulator (SESC). Results reveal that our queueing theoretic model qualitatively evaluates multi-core architectures accurately with an average difference of 5.6% as compared to the architectures’ evaluations from the SESC simulator. Our modeling approach can be used for performance per watt and performance per unit area characterizations of multi-core embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.