n沟6H-SiC MOSFET阈值电压的温度特性模拟与分析

分析了n沟6H—SiCMOSFET的杂质不完全离化和SiO2—SiC界面存在大量界面陷阱等问题，研究了影响6H—SiCMOSFET器件阅值电压温度特性的诸因素。通过解析式计算和MEDICI软件模拟，得到了多种因素共同作用下的器件闪值电压的温度特性。研究表明，体内杂质的不完全离化、表面空间电荷层中的杂质离化程度和特定分布的界面电荷，对阅值电压的温度特性有显著的影响。     

Determination of interface and bulk traps in the subthreshold region of polycrystalline silicon thin-film transistors

A simple method to determine the Interface and bulk density of states in polycrystalline silicon thin-film transistors is presented. The energy distribution of the interface trap density has been extracted from analysis of the transfer characteristics in the subthreshold region of operation. Using the obtained interface state distribution, the energy distribution of the bulk traps has been determined by fitting the surface potential at each gate voltage with an analytical theoretical model. Both interface and bulk traps were found to consist of deep states with constant density near the mid-gap and band-tails with density increasing exponentially with the energy when the trap energy approaches the conduction band-edge.     

Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

A two-dimensional numerical solution of electrostatic potential and electric field profiles are presented for lightly doped nano-scale Double-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistor (DG-MOSFET). We have developed quasi-static (QS) model for evaluating bulk and inversion charges based on symmetric linearization model. We have also shown the non-quasi-static (NQS) effect on the charge due to a time varying gate voltage. It is seen that various symmetries of DG-MOSFET characteristics with respect to source/drain interchange is maintained in quasi-static as well as non-quasi-static version of the symmetrically linearized model. The variation of the threshold voltage with the varying width of the device is evaluated and presented. The results have been compared and contrasted with reported analytical model for QS condition for the purpose of verification of the model. The variation of threshold voltage along the width of the device is also predicted. This numerical model can be extended to analyze the transport phenomenon in sub 30 nm channel length DG-MOSFETs.     

A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates

A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.     

Erasing characteristics of a thin-film electroluminescent ZnS:Mn faceplate

Experimental results show that it is not possible to erase completely electroluminescent ZnS:Mn memory device biased near the threshold voltage, for erase time pause of the order of tens of milliseconds, by either the "bulk" erase or the "selective electron beam" erase method. The selective erase requires a time delay before reimposition of the normal sustain voltage to allow a significant decay of persistent beam-induced conductivity. The process of bulk erasure can be explained satisfactorily by a theoretical model which treats the macroscopic electroluminescent region as an ensemble of bistable microscopic filaments, with each filament having a field-dependent coefficient for the recombination of the deep hole traps with the electron flux. The simple assumption of a Gaussian distribution of extinction voltages for the ensemble of microscopic filaments is sufficient to explain the experimental results, except near the threshold voltage where the measured curves show oscillatory features which remain unexplained.     

后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性研究

本文对后栅工艺高k/金属栅结构NMOSFET偏压温度不稳定性特性进行了研究。在加速应力电压和高温条件下,NMOSFET的阈值电压的退化与时间呈幂指数关系。然而幂指数随应力电压的增大而减小;在本文中,应力从0.6V到12V,幂指数则相应的由0.26减小到0.16。通过对应力前后器件的亚阈值特性分析,在应力过程中没有界面态产生。根据实验数据提取到数值为0.1eV的热激活能,表明偏压温度不稳定性是由栅介质中预先存在的陷阱俘获从衬底隧穿的电子造成的。恢复阶段的测试显示阈值电压的退化与对数时间呈线性关系,同时可以用确定的数学表达式来表明其与应力电压和温度之间的关系。     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

带温度补偿的6H-SiC PMOS模拟与分析

提出了一个在较宽温度范围内能精确描述6H-SiC PMOS性能的器件模型。该模型将阈值电压、沟道迁移率、体漏电流、源漏薄层电阻的温度效应等效为相应的补偿电流源,并计入界面态电荷高斯分布模型及体内Poole-Frenkel效应。模拟结果表明,阈值电压是引起高温条件下输出电流变化的主要因素,同时随着温度的升高,由于体内缺陷的存在导致体漏电流所占比例不断增大,逐渐成为Ids的重要组成部分。     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

二维短沟道MOSFET阈值电压分析模型

随着器件尺寸的进一步减小,由量子效应导致的能带分裂对MOSFET中阈值电压特性的影响变得越来越重要.提出了一个包含量子效应(QME)的短沟道金属氧化物场效应晶体管(MOSFET)分析的阈值电压模型,该模型建立在求解包含量子校正的泊松方程的基础上.分析在泊松方程中考虑量子效应后建立的分析的阈值电压模型可知:随着器件尺寸的减小,由量子效应和短沟道效应引起的阈值电压的升高变得越来越严重.本模型的优点是没有引入额外的物理参数.     

An analytical expression for the threshold voltage of a small geometry MOSFET

A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

Statistical aspects of reliability in bulk MOSFETs with multiple defect states and random discrete dopants

We present a 3D statistical simulation study of the distribution of fractional current change and threshold voltage shift in an ensemble of realistic 35 nm bulk MOSFETs caused by charge trapping on stress generated defect states at the Si/SiO₂ interface, taking simultaneously into account random discrete dopant in the transistors and the statistically realistic distribution of traps. The role of strategically positioned defect states and their statistical distribution in generating ‘anomalously’ large current and threshold voltage change in devices with microscopically different discrete doping configurations is highlighted.     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

Threshold Voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation

A threshold voltage model for mesa-isolated fully depleted silicon-on-insulator (FDSOI) MOSFETs, based on the analytical solution of three-dimensional (3-D) Poisson's equation is presented for the first time in this paper. The separation of variables technique is used to solve the 3-D Poisson's equation analytically with appropriate boundary conditions. Simple and accurate analytical expressions for the threshold voltage of the front and the back gate are derived. The model is able to predict short channel as well as narrow width effects in mesa-isolated FDSOI MOSFETs. The model is validated by comparing with the experimental results as well as with the numerical results available in the literature.     

GaAs PHEMT器件的退化特性及可靠性表征方法

测量了应力前后Ga As PHEMT器件电特性的退化,指出了Ga As PHEMT阈值电压的退化由两个原因引起.栅极下Al Ga As层深能级的空穴积累可以解释阈值电压漂移中暂时性的、可恢复的那部分,积累在栅金属与半导体之间界面层的空穴可以解释阈值电压漂移中永久性的漂移.空穴积累来源于场助作用下电子的退陷和沟道中碰撞电离产生的空穴向栅极流动时被俘获.对高场下碰撞电离率的实验曲线进行拟合,得到碰撞电离率与器件沟道电场峰值的量化关系,可以对Ga As PHEMT器件的电性能和可靠性进行评估     

存在界面陷阱的n沟6H-SiC MOSFET温度特性研究

利用二维器件仿真软件 MEDICI建立了具有指数分布界面陷阱的 n沟 6H-Si C场效应晶体管的结构模型和物理模型 ,通过模拟研究 ,分析和讨论了界面陷阱对器件阈值电压、跨导及其温度特性的影响。