A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.      

The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses $({T}_{rm SOI})$ on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker ${T}_{rm SOI}$ device, the thinner ${T}_{rm SOI}$ device with high-strain CESL possesses a higher interface trap $({N}_{rm it})$ density, leading to degradation in the device performance. On the other hand, however, the thicker ${T}_{rm SOI}$ device reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker ${T}_{rm SOI}$ has a higher bulk oxide trap $({N}_{rm BOT})$ density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker ${T}_{rm SOI}$ devices in this strain technology.      

A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-$Q$ above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high- $Q$ above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input 1 dB compression point $({rm IP}_{{-}1~{rm dB}})$ is ${- 9.5}~{rm dBm}$ and the input referred third-order intercept point $(P _{rm IIP3})$ is ${+ 2.25}~{rm dBm}$. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Improved Microwave Noise Performance by SiN Passivation in AlGaN/GaN HEMTs on Si

Effects of silicon nitride (SiN) surface passivation by plasma enhanced chemical vapor deposition (PECVD) on microwave noise characteristics of AlGaN/GaN HEMTs on high-resistivity silicon (HR-Si) substrate have been investigated. About 25% improvement in the minimum noise figure $(NF_{min})$ (0.52 dB, from 2.03 dB to 1.51 dB) and 10% in the associate gain $(G_{rm a})$ (1.0 dB, from 10.3 dB to 11.3 dB) were observed after passivation. The equivalent circuit parameters and noise source parameters (including channel noise coefficient $(P)$, gate noise coefficient $(R)$, and their correlation coefficient $(C)$ ) were extracted. $P$ , $R$ and $C$ all increased after passivation and the increase of C contributes to the decrease of the noise figure. It was found that the improved microwave small signal and noise performance is mainly due to the increase of the intrinsic transconductance $(g_{{rm m}0})$ and the decrease of the extrinsic source resistance $(R_{rm s})$.      

A 2.4 GHz Current-Reused CMOS Balun-Mixer

A 0.13 $mu{rm m}$ CMOS 2.4 GHz balun-mixer is proposed, where a current-reused noise-canceling topology is adopted as the transconductance stage to reduce dc power consumption. After frequency conversion, noise-cancellation is achieved only when a specified condition is satisfied, but single-to-differential signal conversion is inherently obtained by the mixer operation. The fabricated chip shows a conversion gain of 13.5 dB, a single-side-band (SSB) noise figure of 8 dB, and an input-referred ${rm IP}_{3}$ of ${- 6}~{rm dBm}$, while consuming only 3.5 mA from a 1.5 V supply voltage.      

A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

This paper describes a reconfigurable analog baseband (ABB) for a software-defined radio (SDR). A wide variety of filter characteristics needed for SDR can be obtained by a reconfigurable filter based on a newly developed duty-cycle controlled discrete-time transconductor. The ABB, implemented in a 90 nm CMOS process, provides second- and fourth-order Butterworth, Chebyshev, and elliptic responses with bandwidths from 400 kHz to 30 MHz. The chip draws only 12 mA and achieves a P$_{rm 1dB}$ of $+7~hbox{dBm}$ with a 1.0 V supply. The input-referred integrated in-band noise is $0.31~{rm m}{rm V}_{rm rms}$ and the die area is as small as $0.57~{hbox{mm}}^{2}$.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

Photosensitive Inverter and Ring Oscillator With Pseudodepletion Mode Load for LCD Applications

Photosensitive inverters and ring oscillators (ROs) with pseudodepletion mode loads (PDMLs) were integrated in LCD panels using conventional mass production processes. The delay time $(t_{rm pd})$ of five-stage ROs with PDML reduced from 204.3 $mu hbox{s}$ under dark to 16.3 $muhbox{s}$ under backlight illumination of 20 000 lx. The oscillation frequency exhibited a power-law dependence $(f_{rm osc} infty hbox{IL}^{gamma})$ on the backlight illuminance with the extracted fitting parameter $gamma = hbox{0.447}$ at room temperature.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.      

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of $pm 1~{rm dB}$ at an overall gain of $-2~{rm dB}$, an input reflection below $-12~{rm dB}$, an output reflection below $-18~{rm dB}$, a group delay variation below 6 ps and a $-1~{rm dB}$ input compression point of more than 1 dBm in both switching states over the full 3.1–10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a $0.8~mu {rm m}$ Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of $510 times 490~mu{rm m}^{2}$ , including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.      

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz ${rm f}_{rm T}$ and ${rm f}_{max}$ 0.18 $mu$m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and ${-}3.9$ dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 $mu$m $,times,$424 $mu$m (0.272 mm $^{2}$) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

Electrical Instability of RF Sputter Amorphous In-Ga-Zn-O Thin-Film Transistors

Bias-temperature-stress (BTS) induced electrical instability of the RF sputter amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) was investigated. Both positive and negative BTS were applied and found to primarily cause a positive and negative voltage shift in transfer $(I _{rm DS} -V _{rm GS})$ characteristics, respectively. The time evolution of bulk-state density $(N _{rm BS})$ and characteristic temperature of the conduction-band-tail-states $(T _{G})$ are extracted. Since both values showed only minor changes after BTS, the results imply that observed shift in TFT $I _{rm DS} -V _{rm GS}$ curves were primarily due to channel charge injection/trapping rather than defect states creation. We also demonstrated the validity of using stretch-exponential equation to model both positive and negative BTS induced threshold voltage shift $(Delta V _{rm th})$ of the a-IGZO TFTs. Stress voltage and temperature dependence of $Delta V _{rm th}$ evolution are described.      

Effects of Plasma-Induced Si Recess Structure on n-MOSFET Performance Degradation

Performance degradation of n-MOSFETs with plasma-induced recess structure was investigated. The depth of Si recess $(d_{R})$ was estimated from the experiments by using Ar gas plasmas. We propose an analytical model by assuming that the damage layer was formed during an offset spacer etch. A linear relationship between threshold voltage shift $(Delta V_{rm th})$ and $d_{R}$ was found. Device simulations were also performed for n-MOSFETs with various $(d_{R})$. Both $vertDelta V_{rm th}vert$ and off-state leakage current increased with an increase in $d_{R}$ . The increase in $vertDelta V_{rm th}vert$ becomes larger for smaller gate length. The results from device simulations are consistent with the analytical model. These findings imply that the Si recess structure induced by plasma damage enhances $V_{rm th}$-variability in future devices.