FIR digital filter design techniques using weighted Chebyshev approximation

This paper discusses the various approaches to designing FIR digital filters using the theory of weighted Chebyshev approximation. The different design techniques are explained and compared on the basis of their capabilities and limitations. The relationships between filter parameters are briefly discussed for the case of low-pass filters. Extensions of the theory to the problems of magnitude and complex approximation are also included, as are some recent results on the design of two-dimensional FIR filters by transformation.     

Generalized digital Butterworth filter design

This correspondence introduces a new class of infinite impulse response (IIR) digital filters that unifies the classical digital Butterworth filter and the well-known maximally flat FIR filter. New closed-form expressions are provided, and a straightforward design technique is described. The new IIR digital filters have more zeros than poles (away from the origin), and their (monotonic) square magnitude frequency responses are maximally flat at ω=0 and at ω=π. Another result of the correspondence is that for a specified cutoff frequency and a specified number of zeros, there is only one valid way in which to split the zeros between z=-1 and the passband. This technique also permits continuous variation of the cutoff frequency. IIR filters having more zeros than poles are of interest because often, to obtain a good tradeoff between performance and implementation complexity, just a few poles are best     

数字滤波器在数字信号处理中的应用设计

在信号处理中,滤波占有十分重要的地位.数字滤波是数字信号处理的基本方法,以FIR滤波器为基础,利用MATLB程序设计语言对低通FIR数字滤波器进行了有效的设计,应用DSP 汇编语言编程实现了该滤波器.     

Extended-window interpolation applied to digital filter design

This paper develops a procedure for the design of frequency-selective interpolation operators that can be computed and saved once and for all. These operators are used to design real-time digital operators: interpolators, FIR differentiators, IIR filters, and composed interpolation and filtering operators. Each real-time operator is a matrix relating sets of data points to sets of interpolated values. Since these matrices are characterized by low norms, they permit reduced-word implementations, and are suitable for real-time processing with array processors and massively parallel machines. The design of the interpolation operators uses windows that, unlike traditional approaches, extend beyond the data interval up to the length permitted by the dimensionality theorem. A new form of the dimensionality theorem is used to minimize the minimax interpolation error within a predetermined frequency range, which may be either the passband of the antialiasing filter or the passband of an analog prototype filter. The main application presented in the paper is the design of combined digital filters and interpolators, which will be referred to as interpolating filters. The frequency responses of such filters, as well as the interpolated time responses, almost coincide with those of the corresponding analog prototypes     

IIR数字滤波器的研究与设计

文中探讨了利用模拟滤波器设计IIR数字滤波器过程中的转换方法,脉冲响应不变法和双线性变换法,在MATLAB中以两种方法设计了数字巴特沃思低通滤波器。探讨了MATLAB中非低通数字滤波器的完全工具函数设计法和分步函数设计法,以上述方法分别设计了切比雪夫I型数字低通、高通、带通、带阻滤波器。     

基于DSP Builder的数字滤波器设计与实现

现场可编程门阵列（FPGA）器件广泛用于数字信号处理领域,而使用VHDL或VerilogHDL语言进行设计比较复杂。提出一种采用FDATOOL工具和DSP Builder实现FIR滤波器的设计方案,按照MATLAB/Simulink/DSP Builder/QuartusII设计流程,使用FDATOOL工具可以实时调整滤波器的参数,采用DSP Builder设计了一个16阶FIR低通滤波器模型,并完成了仿真与验证,将模型转换生成VHDL代码,实现了基于FPGA的数字滤波器的设计。结果表明,该方法简单易行,易修改与移植,可满足设计要求,它验证了采用DSP Builder实现数字滤波器设计的独特优势。     

Comments on "FIR digital filter design techniques using weighted Chebyshev approximation"

The history of the FIR filter approximation problem, as recently presented by Rabiner, McClellan, and Parks, is deficient in some areas and misleading in others. Some corrections are suggested. In addition to a brief discussion of different approaches to the design of FIR digital filters, areas into which present methods can be readily extended are outlined. The relationship between the parks and McClellan method and the upper and lower function method is presented.     

I.I.R. digital filter design using constrained optimisation techniques

A new design method for all-pole infinite impulse response (i.i.r.) digital filters is introduced. The method involves minimising the area between the ideal lowpass filter response in the passhand and the actual passband response, subject to a quadratic constraint which ensures filter realisability. A unique solution is obtained to the minimisation which relates the filter weights to the eigenvector of a Toeplitz matrix. The filters are seen to have a small ripple in the passhand and a sharp cutoff in the stopband.     

Complex notch filter design using allpass filter

Complex coefficient IIR notch filter design problems are investigated. The specification of a notch filter is first transformed into that of an allpass filter. An effective approach to the design of this desired allpass filter is developed. The realisation of the proposed notch filter is equivalent to the realisation of an allpass filter. Owing to the mirror-image symmetry relation between the numerator and denominator polynomials of allpass filters, the notch filter can be realised by a computationally efficient lattice structure with very low sensitivity     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

Partial spectrum reconstruction using digital filter banks

The problem of reconstructing a part of the spectrum is reduced to designing the filter bank to satisfy a set of conditions. For the case considered here, these conditions cannot be satisfied simultaneously, so perfect reconstruction is not possible. The necessary and sufficient conditions on the filters so that the resulting filter bank cancels most alias components are found. Such filter banks are called partial alias cancellation filter banks. The product of the polyphase transfer matrices of these filter banks must be a block pseudocirculant matrix. An algorithm design procedure is discussed, and examples are given to demonstrate the theory     

Increased precision digital filter coefficients using digitaldither

The DF1 (direct form 1) IIR filter structure is the most common structure employed in audio applications. The author explores the application of digital dither to increase the precision of filter coefficients allowing up to double precision performance to be achieved with single precision arithmetic. This realisation provides a versatile DF1 realisation suitable for many applications     

In the optimum design of the block adaptive FIR digital filter

A general optimum block adaptive (GOBA) algorithm for adaptive FIR (finite impulse response) filtering is presented. In this algorithm, the correction terms for the filter coefficients in each block, instead of the convergence factors, are optimized in a least squares sense. There are no constraints on the block length L and the filter tap number N. It is shown that the GOBA algorithm is reduced to the normalized LMS algorithm when L⩾N. The convergence of the GOBA algorithm can be assured if the correlation matrix of the input signal is positive definite. Computer simulations based on an efficient computing procedure confirm that the GOBA algorithm achieves faster convergence with slightly degraded convergence accuracy in stationary environments and better weight tracking capability in nonstationary environments as compared to existing block adaptive algorithms with no constraints on L and N     

Optical notch filter design based on digital signal processing

Based on digital signal processing theory,a novel method of designing optical notch filter is proposed for Mach-Zehnder interferometer with cascaded optical fiber rings coupled structure.The method is simple and effective,and it can be used to implement the designing of the optical notch filter which has arbitrary number of notch points in one free spectrum range(FSR).A design example of notch filter based on cascaded single-fiber-rings is given.On this basis,an improved cascaded double-fiber-ri...     

New integer programming scheme for nonrecursive digital filter design

A new mixed-integer linear programming objective function for optimising an f.i.r. linear-phase digital filter is presented. In comparison with the conventional objective function, the new one has the advantages of reducing the number of delays and/or the coefficient wordlength.     

High-performance active polyphase filter design for digital TV tuner

This paper presents the polyphase filter design for the tuner of DTV front-end system. The polyphase filter is designed with an active circuit to improve the chip performance. Most of passive capacitor and resistor components are replaced with MOS transistors. The proposed method not only can reduce the chip area but also gain the signal level. For the prototyping implementation, the current channel bands in Taiwan are referred, which the frequency range is from 530 to 602 MHz for DTV programs. In experiments, the polyphase filter can achieve 85 dB for the image rejection in the center frequency. The main signal can be gained about 2-5 dB without using extra amplifier. The chip size is about 0.09 mm², and the average power dissipation is about 15 mW, when the chip technology employed TSMC 0.35 μm CMOS process. The proposed chip outperforms with less area and higher gain.     

Approximate realization of digital fractional forward operator using digital IIR filter

In this paper, a simple and an efficient approach for approximating the digital fractional forward operator z ^m (0?<?m?<?1) using digital infinite impulse response (IIR) filter is proposed. In this method, the coefficients of the closed form digital IIR filter derived for the approximation of the fractional forward operator, in a given frequency band, are based on approximation of fractional order systems. First, analog rational function approximation, in a given frequency band, of the fractional power zero (FPZ) is given. Then, the forward difference generating function is used to obtain a closed form IIR digital filter equivalent of the continuous FPZ, which approximates the digital fractional forward operator. Finally, illustrative examples have been presented to illustrate the effectiveness of the proposed design technique of the fractional forward operator z ^m approximation and its use in performing a fractional m-step prediction.     

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

Novel digital filter implementations using hybrid RNS-binary arithmetic

The implementation of a FIR filter using a new hybrid RNS-binary arithmetic is presented for the first time. In the new arithmetic, the data samples are represented using RNS, and hence the carry free advantage of RNS computations is retained. However, the computation performed for each modulo is implemented using conventional binary arithmetic elements which overcome the drawback of ROM-based RNS arithmetic elements that become inefficient for large moduli. The conventional binary arithmetic elements are also faster and require less area than existing memoryless RNS arithmetic elements. It is shown that the filter structures based on the new arithmetic have better performance than those based on either the conventional binary or conventional RNS arithmetic for large moduli.