Sb-modified growth of stacked Ge/Si(100) quantum dots

We report on the Sb induced modifications of the morphology of self assembled Ge/Si(100) quantum dot stacks in a Si matrix grown by a molecular beam epitaxy. It is shown that the size of the quantum dots in the stack and the Si spacer layer uniformity inside the stack are regulated by the amount of deposited Sb. We consider the thin Sb layer at the Ge/Si growth interface as a factor limiting the surface migration of Si and Ge ad-atoms. The surface diffusion coefficients of Si ad-atom on uncovered pyramid shaped Ge island and on a Ge island covered by a single monolayer of Sb are estimated to be 2.4 μm²s⁻¹ and 2.3 × 10⁻⁴ μm²s⁻¹ at a temperature of 600 °C, correspondingly. Based on this remarkable reduction of surface diffusion the morphology of the surface can be preserved when the growth is continued after the single monolayer of Sb is at the surface.     

Laser assisted formation of binary and ternary Ge/Si/Sn alloys

Binary and ternary Si/Ge/Sn alloys were epitaxially grown on virtual Germanium buffer layers using pulsed laser induced epitaxy with a 193 nm Excimer laser source. The role of the processing parameters on the intermixing of the components (Sn, Ge and Si) has been studied. Characterization of the resulting Ge_1 − xSn_x and Si_{1 − y − x}Ge_ySn_x alloys yield up to 1% Sn concentration in substitutional sites of the Ge or SiGe matrix.     

Comparison of Ohmic contact resistances of n- and p-type Ge source/drain and their impact on transport characteristics of Ge metal oxide semiconductor field effect transistors

We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal-oxide-semiconductor field-effect transistor). The poor electron transport property is primarily attributed to the low dopant activation efficiency and high contact resistance. Results are supported by analyzing source/drain Ohmic metal contacts to n-type Ge using the transmission line method. Ni contacts to Ge nMOSFETs exhibit specific contact resistances of 10^− 3-10^− 5 Ω cm², which is significantly higher than the 10^− 7-10^− 8 Ω cm² of Ni contacts to Ge pMOSFETs. The high resistance of Ni Ohmic contacts to n-type Ge is attributed mainly to insufficient dopant activation in Ge (or high sheet resistance) and a high tunneling barrier. Results obtained in this work identify one of the root causes of the lower than expected Ge nMOSFET transport issue, advancing high mobility Ge channel technology.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

Extended deep level defects in Ge-condensed SiGe-on-Insulator structures fabricated using proton and helium implantations

SiGe-on-Insulator (SGOI) structures were created using the Ge condensation method, where an oxidation process is performed on the SiGe/Si structure. This method involves rapid thermal chemical vapor deposition and H⁺/He⁺ ion-implantations. Deep level defects in these structures were investigated using deep level transient spectroscopy (DLTS) by varying the pulse injection time. According to the DLTS measurements, a deep level defect induced during the Ge condensation process was found at 0.28 eV above the valence band with a capture cross section of 2.67 × 10^− 17 cm², two extended deep levels were also found at 0.54 eV and 0.42 eV above the valence band with capture cross sections of 3.17 × 10^− 14 cm² and 0.96 × 10^− 15 cm², respectively. In the SGOI samples with ion-implantation, the densities of the newly generated defects as well as the existing defects were decreased effectively. Furthermore, the Coulomb barrier heights of the extended deep level defects were drastically reduced. Thus, we suggest that the Ge condensation method with H⁺ ion implantation could reduce deep level defects generated from the condensation and control the electrical properties of the condensed SiGe layers.     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

Radiation damage of Si1-xGex S/D p-type metal oxide semiconductor field effect transistor with different Ge concentrations

The 2-MeV electron radiation damage of Si_1-xGe_x source/drain (S/D) p-type metal oxide semiconductor field effect transistor (p-MOSFET) with different Ge concentrations is studied. After irradiation at fluences below 2 × 10¹⁷ e/cm², the drain current and the maximum hole mobility decrease with increasing electron fluence for all Ge concentrations. It suggests that lattice defects are introduced by electron irradiation. In the case of Si_1-xGe_x S/D p-MOSFET, there are two locations for lattice defects, namely, the Si channel and SiGe stressor regions (S/D). Below 2 × 10¹⁷ e/cm² irradiation, no clear correlation between the radiation degradation and Ge concentration has been observed. It suggests that this degradation is mainly due to lattice defects in the Si channel, and the effects of the compressive-strain induced by the SiGe stressors on the enhancement of the hole mobility still remains after irradiation at 2 × 10¹⁷ e/cm². In the case of 5 × 10¹⁷ e/cm² irradiation, the drain current drastically decreases after irradiation for all Ge concentrations. Moreover, after 5 × 10¹⁷ e/cm² irradiation, the maximum hole mobility of x = 0.2 is close to x = 0, and in the case of x = 0.3, the maximum hole mobility drastically decreases. This fact suggests the contributions of the lattice defects, which are in the SiGe stressors, are prominent after 5 × 10¹⁷ e/cm² irradiation and dependent on Ge concentration. In addition, it provides evidence that the compressive strain in the Si-channel is relaxed by high fluence electron irradiation.     

Low temperature (~ 250 °C) layer exchange crystallization of Si1 − xGex (x = 1-0) on insulator for advanced flexible devices

Low-temperature (~ 250 °C) layer exchange crystallization of poly-Si_1 − xGe_x (x = 1-0) films on insulators has been investigated for realization of advanced flexible devices. We propose utilization of Au as catalyst to enhance the crystallization at low temperatures. By annealing (~ 250 °C, 20 h) of the a-Si_1 − xGe_x (x = 1-0)/Au stacked structures formed on insulating substrates, the SiGe and Au layers exchange their positions, and Au/poly-SiGe stacked structures are obtained. The Ge fractions of the obtained poly-SiGe layers are identical to that of the initial a-SiGe layers, and there is no Si or Ge segregation. This low temperature crystallization technique enables poly-SiGe films on plastic substrates, which are essential to realize advanced flexible devices.     

Low threading dislocation Ge on Si by combining deposition and etching

Blanket and selective Ge growth on Si is investigated using reduced pressure chemical vapor deposition. To reduce the threading dislocation density (TDD) at low thickness, Ge deposition with cyclic annealing followed by HCl etching is performed. In the case of blanket Ge deposition, a TDD of 1.3 × 10⁶ cm^− 2 is obtained, when the Ge layer is etched back from 4.5 μm thickness to 1.8 μm. The TDD is not increased relative to the situation before etching. The root mean square of roughness of the 1.8 μm thick Ge is about 0.46 nm, which is of the same level as before HCl etching. Further etching shows increased surface roughness caused by non-uniform strain distribution near the interface due to misfit dislocations and threading dislocations. The TDD also becomes higher because the etchfront of Ge reaches areas with high dislocation density near the interface. In the case of selective Ge growth, a slightly lower TDD is observed in smaller windows caused by a weak pattern size dependence on Ge thickness. A significant decrease of TDD of selectively grown Ge is also observed by increasing the Ge thickness. An about 10 times lower TDD at the same Ge thickness is demonstrated by applying a combination of deposition and etching processes during selective Ge growth.     

High strain embedded-SiGe via low temperature reduced pressure chemical vapor deposition

Performance improvement of strained p-type metal oxide semiconductor field effect transistors (p-MOSFETs) via embedded SiGe (e-SiGe) is well established. Strain scaling of p-MOSFETs since 90 nm complementary metal oxide semiconductor node has been accomplished by increasing Ge content in e-SiGe from nominally < 20% in 90 nm p-MOSFETs to > 35% Ge in 32 nm p-MOSFETs. Further strain enhancement for 22 nm and beyond p-MOSFETs is required due to disproportionate reduction in device area per generation caused by non-scaled gate length. Relaxation of SiGe with > 35% Ge during epitaxial growth and subsequent processing is a major concern. Specifically low temperature growth is required to achieve meta-stable pseudomorphic SiGe film with high Ge%. Currently, selective SiGe epitaxial film in reduced pressure chemical vapor deposition (RPCVD) epitaxy is grown with conventional Si gas precursors and co-flow etch using HCl at temperatures higher than 625 °C. At temperatures lower than 625 °C in RPCVD epitaxy, however, HCl has negligible etch capability making selectivity difficult to achieve during epitaxial growth. Hence, cyclic deposit and etch epitaxial growth in conjunction with a low temperature etching chemistry is desirable to achieve selectivity at temperatures lower than 625 °C. In this paper, we apply the above concept to achieve selective growth of high strain SiGe (> 35%) at 500 °C on test patterns corresponding to 65 nm node. SiGe is grown non-selectively first at 500 °C with high order of silane as Si source, and Germane as Ge source followed by an etching chemistry also at 500 °C to achieve selectivity. In addition, the growth rate of SiGe epitaxial film and the Ge concentration in the deposited epitaxial film were studied as a function of Si precursor flow; the effect of HCl introduction on Ge concentration and film growth rate was discussed.     

Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

Si/SiGe hetero-junction solar cell with optimization design and theoretical analysis

Performances of solar cells, such as short circuit current density, open-circuit voltage, fill factor, and efficiency of solar cells on the multi-crystalline (mc)-SiGe on the Si with different Ge contents, are compared and investigated in this paper. The average Ge concentration was varied from 0% to ~ 20%. Appropriate addition of Ge in crystal Si is a very effective method to enhance the short circuit current density without degrading the open-circuit voltage owing to the modulation of the SiGe band-gap. The band-gap of the SiGe can be extracted by electron-hole plasma (EHP) model. With an optimization of Ge content and clean process condition, the overall efficiency of a Si/SiGe hetero-junction solar cell with Ge content of 8% is found to be ~ 16% and ~ 4% improvement achieved, as compared to the control multi-crystalline (mc)-Si solar cell. The theoretical simulations and analyses can help design the high efficiency Si/SiGe hetero-junction solar cell.     

Properties of La0.75Sr0.25MnO3 films grown on Si substrate with Si1−xGex and Si1−yCy buffer layers

The structural and electrical properties of La_0.75Sr_0.25MnO₃ (LSMO) film on Bi₄Ti₃O₁₂ (BTO)/CeO₂/YSZ buffered Si_1−xGe_x/Si (0.05 ≤ x ≤ 0.2 for compressive strain), blank Si, and Si_1−yC_y/Si (y = 0.01 for tensile) were studied. X-ray high resolution reciprocal lattice mapping (HRRLM) and atomic force microscopy (AFM) show that structural properties of LSMO and buffer oxide layers are strongly related to the strain induced by amount of Ge and C contents. The RMS roughness of LSMO on Si_1−xGe_x/Si has a tendency to increase with increasing of Ge content. Electrical properties of LSMO film with Ge content up to 10% are slightly improved compared to blank Si whereas higher resistivity values were obtained for the samples with higher Ge content.     

Room temperature deposited vanadium oxide thin films for uncooled infrared detectors

We demonstrate the room temperature deposition of vanadium oxide thin films by pulsed laser deposition (PLD) technique for application as the thermal sensing layer in uncooled infrared (IR) detectors. The films exhibit temperature coefficient of resistance (TCR) of 2.8%/K implies promising application in uncooled IR detectors. A 2-D array of 10-element test microbolometer is fabricated without thermal isolation structure. The IR response of the microbolometer is measured in the spectral range 8-13 μm. The detectivity and the responsivity are determined as ∼6×10⁵ cm Hz^1/2/W and 36 V/W, respectively, at 10 Hz of the chopper frequency with 50 μA bias current for a thermal conductance G∼10-3 W/K between the thermal sensing layer and the substrate. By extrapolating with the data of a typical thermally isolated microbolometer (G∼10⁻⁷ W/K), the projected responsivity is found to be around 10⁴ V/W, which well compares with the reported values.     

Electrical and structural properties of Ta-N thin film and Ta/Ta-N multilayer for embedded resistor

Ta/Ta-N multilayer has been developed to control temperature coefficient of resistance (TCR) in a thin-film embedded resistor with the incorporation of Ta layer (+ TCR) inserted into Ta-N layers (− TCR). Electrical and structural properties of sputtered Ta, Ta-N and the multilayer films were investigated. The stable resistivity value of 0.0065 Ω·cm in β-Ta film was obtained, and phase change from fcc-TaN to orthorhombic Ta₃N₅ in Ta-N films was observed at nitrogen partial pressure of 22%. The multilayer of Si/Ta(60 nm)/Ta₃N₅(104 nm)/Ta(60 nm)/Ta₃N₅(104 nm) showed TCR value of − 284 ppm/K, where TCR of Ta was − 183 ppm/K and that of Ta₃N₅ was − 3193 ppm/K.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

Effect of Germanium content and strain on the formation of extended defects in ion implanted Silicon/Germanium

We studied the evolution of extended defects in relaxed and strained Si and SiGe structures after an amorphising implant. The investigated structures included three relaxed SiGe alloy layers with various Ge contents (20, 35 and 50 at.%), a 40 nm-thick tensely strained Si layer and a 40 nm-thick compressively strained Si_0.8Ge_0.2 layer. Concerning the compositional effects, we found that the increase of Ge concentration in relaxed SiGe structures leads to: (i) an overall decrease of the defect stability and to (ii) an enhanced {311}-to-loops transformation. As for the strain effects, it is found that: (i) Tensile strain (in Si) retards the transformation of {311} defects into loops; (ii) compressive strain (in SiGe) enhances the transformation of {311}s into loops; (iii) in all cases, the overall defect stability is not strongly modified in the presence of strain. The observed results are discussed in terms of the various mechanisms involved, including the increase of the interstitial diffusivity in relaxed SiGe alloys (with respect to Si) and the strain effects on both interstitial equilibrium concentration and defect formation energy.     

Ion channeling study of epitaxy of iron based Heusler alloy films on Ge(111)

We have investigated perfection of atomic rows on iron-based Heusler alloy films on Ge(111) planes by using ion channeling technique in order to find the dominant factors for the perfection. Fe₃Si/Ge(111) and Fe₂CoSi/Ge(111) have a high quality of atomic rows at the heterointerface like that of perfect crystals. Fe_3−xMn_xSi/Ge(111) (x = 0.84, 0.72 and 0.36) interfaces have imperfection of atomic rows which may be controlled by both the lattice mismatch with the Ge substrate and the Mn-Si pairs due to the site disorder in the film with the Mn content x > 0.75. Analysis of axial channeling parameters employed in this study is very useful for quantitative evaluation of perfection of atomic rows at the heterointerface.     

Defect introduction in Ge during inductively coupled plasma etching and Schottky barrier diode fabrication processes

We have etched Sb-doped n-type (111) oriented Ge by inductively coupled plasma (ICP), using argon, and subsequently studied the defects that this process introduced as well as the effect of this etching on Schottky barrier diode quality. Deep level transient spectroscopy (DLTS) revealed that ICP etching introduced only one prominent defect, EP_0.31, in Ge with a level at 0.31 eV below the conduction band. The properties of this defect are different to those of defects introduced by other particle-related processing steps, e.g. sputter deposition and electron beam deposition, that each introduces a different set of defects. DLTS depth profiling revealed the EP_0.31 concentration was a maximum (3.6 × 10¹³ cm^− 3) close to the Ge surface and then it decreased more or less exponentially into the Ge. Annealing at 250 °C reduced the EP_0.31 concentration to below the DLTS detection limit. Finally, current-voltage (I-V) measurements as a function of temperature revealed that the quality of Schottky contacts fabricated on the ICP-etched surfaces was excellent at − 100 K the reverse leakage current at − 1 V was below 10 ¹³ A (the detection limit of our I-V instrumentation).     

Epitaxy of In0.01Ga0.99As on Ge/offcut Si (001) virtual substrate

In_0.01Ga_0.99As thin films free of anti-phase domains were grown on 7° offcut Si (001) substrates using Ge as buffer layers. The Ge layers were grown by ultrahigh vacuum chemical vapor deposition using ‘low/high temperature’ two-step strategy, while the In_0.01Ga_0.99As layers were grown by metal-organic chemical vapor deposition. The etch-pit counting, cross-section and plane-view transmission electron microscopy, room temperature photoluminescence measurements are performed to study the dependence of In_0.01Ga_0.99As quality on the thickness of Ge buffer. The threading dislocation density of Ge layer was found to be inversely proportional to the square root of its thickness. The threading dislocation density of In_0.01Ga_0.99As on 300 nm thick Ge/offcut Si was about 4 × 10⁸ cm^− 2. Higher quality In_0.01Ga_0.99As can be obtained on thicker Ge/offcut Si virtual substrate. We found that the threading dislocations acted as non-radiative recombination centers and deteriorated the luminescence of In_0.01Ga_0.99As remarkably. Secondary ion mass spectrometry measurement indicated as low as 10¹⁶ cm^− 3 Ge unintended doping in In_0.01Ga_0.99As.