共查询到17条相似文献,搜索用时 125 毫秒
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AVS中可变长解码器的硬件设计 总被引:1,自引:0,他引:1
AVS是我国自主制定的音视频编码技术标准。简要介绍AVS标准视频压缩部分的特点,重点研究AVS可变长熵解码的原理和技术方法并进行优化,主要采用并行解码结构以达到实时解码。在此基础上提出了一种针对AVS视频编码标准的变长码——指数哥伦布码解码的硬件设计结构,最后给出实现该硬件结构对应FPGA实验仿真结果。 相似文献
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AVS编解码器采用环路滤波去除块效应来提高图像质量,而环路滤波复杂度高、运算量大,且滤波过程数据访问频繁,严重影响了代码的执行效率.为提高解码速率,通过分析滤波算法特点,调整滤波结构,优化滤波算法,部分代码采用DSP汇编语言.结果表明与传统的C相比,缩短了代码运行时间,提高了执行速度,达到实时解码的要求. 相似文献
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《Signal Processing: Image Communication》2009,24(4):312-323
AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform-independent software package with macroblock-based (MB-based) architecture is proposed to facilitate AVS video standard implementation on embedded system. Compared with the frame-based architecture, which is commonly utilized for PC platform oriented video applications, the MB-based decoder performs all of the decoding processes, except the high-level syntax parsing, in a set of MB-based buffers with adequate size for saving the information of the current MB and the neighboring reference MBs to minimize the on-chip memory and to save the time consumed in on-chip/off-chip data transfer. By modifying the data flow and decoding hierarchy, simulating the data transfer between the on-chip memory and the off-chip memory, and modularizing the buffer definition and management for low-level decoding kernels, the MB-based system architecture provides over 80% reduction in on-chip memory compared to the frame-based architecture when decoding 720p sequences. The storage complexity is also analyzed by referencing the performance evaluation of the MB-based decoder. The MB-based decoder implementation provides an efficient reference to facilitate development of AVS applications on embedded system. The complexity analysis provides rough storage complexity requirements for AVS video standard implementation and optimization. 相似文献
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Bit-estimate based decoding for vector quantization over noisychannels with intersymbol interference
We introduce new techniques for quantization over noisy channels with intersymbol interference. We focus on the decoding problem, and present a decoder structure that allows the decoding to be based on soft minimum mean square-error estimates of the transmitted bits. The new bit-estimate based decoder provides a structured lower-complexity approximation of optimal decoding for general codebooks, and for so-called linear mapping codebooks, it is shown that its implementation becomes particularly simple. We investigate decoding based on optimal bit-estimates, and on suboptimal estimates of lower computational complexity. We also consider encoder optimization and combined source-channel code design. Numerical simulations demonstrate that bit-estimate based decoding is able to outperform a two-stage decision-based approach implemented using Viterbi sequence detection plus table look-up source decoding. The simulations also show that decoding based on suboptimal bit-estimates performs well, at a considerably lowered complexity 相似文献
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卷积码编码器和Viterbi译码器的FPGA实现 总被引:1,自引:0,他引:1
Viterbi译码是对卷积码的一种最大似然译码算法。主要介绍卷积码的Viterbi译码器的FPGA(现场可编程门阵列)实现方案。根据卷积码的特点,设计了用寄存器交换法存储幸存路径的模块,充分利用FPGA触发器资源丰富的优点。同时,为使系统在保持同等性能条件下可以高效率实现,对Viterbi译码实现中的数据溢出和输出判决部分进行了优化,处理的结果使得系统的性能和效率都有提高。本设计已基于FPGA实现,译码速度快、延时小。 相似文献