Dual‐Gate Organic Field‐Effect Transistors as Potentiometric Sensors in Aqueous Solution

Buried electrodes and protection of the semiconductor with a thin passivation layer are used to yield dual‐gate organic transducers. The process technology is scaled up to 150‐mm wafers. The transducers are potentiometric sensors where the detection relies on measuring a shift in the threshold voltage caused by changes in the electrochemical potential at the second gate dielectric. Analytes can only be detected within the Debye screening length. The mechanism is assessed by pH measurements. The threshold voltage shift depends on pH as ΔV_th = (C_top/C_bottom) × 58 mV per pH unit, indicating that the sensitivity can be enhanced with respect to conventional ion‐sensitive field‐effect transistors (ISFETs) by adjusting the ratio of the top and bottom gate capacitances. Remaining challenges and opportunities are discussed.     

Gate Capacitance‐Dependent Field‐Effect Mobility in Solution‐Processed Oxide Semiconductor Thin‐Film Transistors

Solution‐processed oxide semiconductors (OSs) used as channel layer have been presented as a solution to the demand for flexible, cheap, and transparent thin‐film transistors (TFTs). In order to produce high‐performance and long‐sustainable portable devices with the solution‐processed OS TFTs, the low‐operational voltage driving current is a key issue. Experimentally, increasing the gate‐insulator capacitances by high‐k dielectrics in the OS TFTs has significantly improved the field‐effect mobility of the OS TFTs. But, methodical examinations of how the field‐effect mobility depends on gate capacitance have not been presented yet. Here, a systematic analysis of the field‐effect mobility on the gate capacitances in the solution‐processed OS TFTs is presented, where the multiple‐trapping‐and‐release and hopping percolation mechanism are used to describe the electrical conductivity of the nanocrystalline and amorphous OSs, respectively. An intuitive single‐piece expression showing how the field‐effect mobility depends on gate capacitance is developed based on the aforementioned mechanisms. The field‐effect mobility, depending on the gate capacitances, of the fabricated ZnO and ZnSnO TFTs clearly follows the theoretical prediction. In addition, the way in which the gate insulator properties (e.g., gate capacitance or dielectric constant) affect the field‐effect mobility maximum in the nanocrystalline ZnO and amorphous ZnSnO TFTs are investigated.     

阶梯栅氧结构的NLDMOS热载流子效应研究

本文对一种新型的阶梯栅氧结构的NLDMOS（Step Gate Oxide NLDMOS , SG-NLDMOS）的热载流子效应进行了研究。采用直流电压应力实验、TCAD仿真、电荷泵测试等方法,对退化现象进行了分析,并提出了退化机制。然后研究了漂移区注入剂量对器件热载流子效应的影响,结果表明低的漂移区注入剂量可以更有效地减小器件导通电阻的退化。     

A Back Gate Tuned PFET VCO

A differential voltage controlled oscillator (VCO) circuit employing PMOS transistors in the gain stage is described. The circuit topology minimizes the amount of fixed parasitic capacitance in the tank circuit. The gain stage transistors employ virtual ground planes for increasing the Q value of the drain-bulk capacitances. Tuning of the oscillation frequency is based on the voltage dependence of the gain stage PFET drain-bulk junction capacitances. The simulation results show that it is possible to increase the tuning range of the 2.8 GHz VCO from 341 MHz to 406 MHz by improving the drain layout design of the gain transistors. Parameters from an industrial 0.35 m CMOS process are used for simulations.     

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO _x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high-κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO _x -Ge quantum dots.     

TOM3 capacitance model: linking large- and small-signal MESFETmodels in SPICE

Improved accuracy in the modeled gate capacitance of GaAs metal-semiconductor field-effect transistors (MESFET's) is obtained in SPICE using conservation of charge in an implanted layer. The gate junction creates a natural partition between mobile and fixed channel charges. Relating the gate charge to the channel current creates gate capacitances dependent upon the channel current derivatives linking the small-signal model to the large-signal equations. Results are illustrated using a depletion-mode MESFET     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Gate metal interdiffusion induced degradation in space-qualified GaAs PHEMTs

While gate metal sinking has been traditionally identified as the primary degradation mechanism in GaAs pseudomorphic high electron mobility transistors (PHEMTs), there is no physical demonstration of gate metal interdiffusion or understanding of the gate metal interdiffusion effect on reliability performance. This paper reviews our results on gate metal interdiffusion in 0.15-μm GaAs PHEMTs subjected to accelerated temperature lifetest. We used the techniques of focused ion beam (FIB), high-resolution energy-dispersive analysis with X-ray (EDX), and scanning transmission electron microscope (STEM). These results substantiate the observed d.c. and RF parametric evolution with respect to reverse gate leakage current (I_g), ideality factor, Schottky barrier height (Φ_BN), transconductance (G_m), I_dss, pinchoff voltage (V_po), S21, and provide insights into the effect of gate metal interdiffusion on reliability performance. The comprehensive understanding of gate metal interdiffusion induced degradation is essential for GaAs PHEMTs due to their widespread military/space applications.     

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.     

High threshold voltage matching performance on gate-all-around MOSFET

For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on Gate-All-Around transistors (GAA) with both doped and undoped channels. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to drastically reduce the dopant induced fluctuations contribution and provides an A_Vt parameter as low as 1.4 mV μm, which is one of the best reported result on MOS transistors.     

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In_0.7Ga_0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system     

On the correlation between radiation-induced oxide- and border-trap effects in the gate-oxide nMOSFET’s

In this study, combined voltage- and frequency-charge pumping techniques were used to investigate the generation and evolution of border-traps in degraded NMOS transistors by using 1.25 MeV ⁶⁰Co γ-rays. In addition, gate length effects on border-trap charge density were discussed. First result, both border- and oxide-trap reveal two behaviors as function of total dose at low dose rate. Primarily, there is an increase of both trapped charges, followed later by a decrease of their net charge. Second result, border-trap presents a strong dependence on designed transistor channel length. Transistors with longer gate lengths exhibit less important border-trap during irradiation than transistors with smaller gate lengths. This is due to differences in the near-interfacial stress. However, the same effects were observed for oxide-traps. These results show a great correlation between radiation-induced border- and oxide-trap behaviors at low dose rate. Therefore, this similarity strengthens the idea that both border- and oxide-trap could have the same defect (E^′).     

Reusable Cellulose‐Based Hydrogel Sticker Film Applied as Gate Dielectric in Paper Electrolyte‐Gated Transistors

A new concept for reusable eco‐friendly hydrogel electrolytes based on cellulose is introduced. The reported electrolytes are designed and engineered through a simple, fast, low‐cost, and eco‐friendly dissolution method of microcrystalline cellulose at low temperature using an aqueous LiOH/urea solvent system. The cellulose solution is combined with carboxymethyl cellulose, followed by the regeneration and simultaneous ion incorporation. The produced free standing cellulose‐based electrolyte films exhibit interesting properties for application in flexible electrochemical devices, such as biosensors or electrolyte‐gated transistors (EGTs), because of their high specific capacitances (4–5 µF cm^?2), transparency, and flexibility. Indium–gallium–zinc‐oxide EGTs on glass with laminated cellulose‐based hydrogel electrolytes (CHEs) as the gate dielectric are produced presenting a low working voltage (<2 V), showing an on–off current ratio (I _on/off) of 10⁶, a subthreshold swing lower than 0.2 V dec^?1, and saturation mobility (μ_Sat) reaching 26 cm² V^?1 s^?1. The flexible CHE‐gated transistors on paper are also demonstrated, which operate at switching frequencies up to 100 Hz. Combining the flexibility of the EGTs on paper with the reusability of the developed CHEs is a breakthrough toward biodegradable advanced functional materials allied with disposable/recyclable and low‐cost electronic devices.     

On the design robustness of threshold logic gates using multi-inputfloating gate MOS transistors

In this paper, the design robustness of logic circuits implemented as threshold logic gates with multi-input floating gate transistors is analyzed. The parameter variations of the basic components, namely the coupling capacitances of the floating gate MOSFETs and the sensing circuits for obtaining full logic levels, are investigated separately using appropriate array test structures. It is found that the dominant mismatch originates from the input offset voltage variations of the sensing circuits. Methods are presented for estimating the yield of a given logic circuit from the measured parameter distributions. The estimations are verified with measured data of a multiplier cell and of the encoding logic in a parallel fingerprint sensor architecture. Considerations are given for robust design of circuits based on threshold logic gates that use floating gate transistors     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

Bulk-tuned Gm–C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom׳s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35 μm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.     

The influence of device physical parameters of HEMT large-signalcharacteristics

The small- and large-signal high-frequency characteristics of submicrometer HEMTs (high-electron-mobility transistors) are analyzed by taking into account parasitic effects such as parallel conduction, fringing capacitances, and substrate leakage. The dependence of large-signal properties on device physical parameters is reported. This includes device gate length, donor layer thickness and doping, and spacer thickness. Satisfactory agreement is shown to exist between theoretically and experimentally obtained device characteristics     

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I_sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I_sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I_sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.     

基于90nm低功耗NMOS工艺射频器件的版图优化

从器件版图结构的布局布线出发,提出了射频器件性能增强的的方法.寄生电容,寄生电阻会明显弱化大尺寸器件的射频性能,通过多个小尺寸单元管子的并联,形成大尺寸器件,从版图的布局布线出发,减小寄生电容,寄生电阻,优化器件结构,提升射频性能.在总栅宽一定时,通过变换单元器件的栅指数与器件的并联数,寻找最佳组合.通过优化,功率增益...     

An appropriate device figure of merit for bipolar CML

The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in current mode logic (CML) circuits, based on minimum propagation delay, is developed. This delay is derived from the large-signal 3-dB cutoff frequency of the CML gate. Results are shown to be applicable for a wide range of device and circuit parameters