The effect of gate metal interdiffusion on reliability performance in GaAs PHEMTs

While Ti metal interdiffusion of Ti-Pt-Au gate metal stacks in GaAs pseudomorphic HEMT (PHEMTs) has been explored, the effect of Ti metal interdiffusion on the reliability performance is still lacking. We use a scanning transmission electron microscopy technique to correlate Ti-metal-InGaAs-channel-separation and Ti-sinking-depth with a threshold voltage V/sub T/. It has been found that Ti-sinking-depth is insensitive to V/sub T/. However, Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus affecting the I/sub dss/ degradation rate. Accordingly, we observe the dependence of /spl Delta/I/sub dss/ on V/sub T/. Devices with less negative V/sub T/ exhibit inferior reliability performance to those devices with more negative V/sub T/. The results provide insight into a critical device parameter, V/sub T/, for optimizing reliability performance based on I/sub dss/ degradation.     

Gate metal interdiffusion induced degradation in space-qualified GaAs PHEMTs

While gate metal sinking has been traditionally identified as the primary degradation mechanism in GaAs pseudomorphic high electron mobility transistors (PHEMTs), there is no physical demonstration of gate metal interdiffusion or understanding of the gate metal interdiffusion effect on reliability performance. This paper reviews our results on gate metal interdiffusion in 0.15-μm GaAs PHEMTs subjected to accelerated temperature lifetest. We used the techniques of focused ion beam (FIB), high-resolution energy-dispersive analysis with X-ray (EDX), and scanning transmission electron microscope (STEM). These results substantiate the observed d.c. and RF parametric evolution with respect to reverse gate leakage current (I_g), ideality factor, Schottky barrier height (Φ_BN), transconductance (G_m), I_dss, pinchoff voltage (V_po), S21, and provide insights into the effect of gate metal interdiffusion on reliability performance. The comprehensive understanding of gate metal interdiffusion induced degradation is essential for GaAs PHEMTs due to their widespread military/space applications.     

GaAs PHEMT器件的失效模式及机理

归纳了GaAs PHEMT器件的几种常见失效模式,并从6个方面分析了PHEMT器件的失效机理:热电子应力退化、氢效应、2DEG结构退化、欧姆接触退化、肖特基接触退化和电迁移.     

Degradation mechanisms of GaAs PHEMTs in high humidity conditions

We have studied the degradation mechanisms of AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) under high humidity conditions (85 °C, 85% relative humidity). The degraded samples under high humidity conditions show a decrease in maximum drain current (I_max) and a positive shift in threshold voltage (V_th). Cross-sectional transmission electron microscopy (TEM) images from the deteriorated devices reveal an existence of damaged recess surface region and a peeling of a passivation film (SiN_x). The secondary ion mass spectrometry (SIMS) depth profile at the interface between the passivation film and AlGaAs surface also indicates the diffusion of gallium (Ga), arsenic (As) and aluminum (Al) into the passivation film. The degradation of PHEMTs arises from mainly two mechanisms: (1) the positive shift in V_th due to stress change under the gate caused by the peeling of passivation films, and (2) the decrease in I_max due to the net carrier concentration reduction of the AlGaAs carrier supply layer caused by the combination of surface degradation at the AlGaAs recess regions and diffusion of Ga, As and Al at the interface between the passivation film and AlGaAs surface. A special treatment just prior to the deposition of SiN_x films on the devices effectively suppresses the degradation of PHEMTs under high humidity conditions without degradation of the high frequency performance.     

单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管

介绍了单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管（PHEMT）工艺。借助栅金属的热处理过程,形成了热稳定性良好的Pt／Ti／Pt／Au栅。AFM照片结果表明Pt金属膜表面非常平整,2nm厚度膜的粗糙度RMS仅为0．172nm。通过实验,我们还得出第一层Pt金属膜的厚度和退火后的下沉深度比大概为1：2。制作的增强型／耗尽型PHEMT的闽值电压（定义于1mA／mm）、最大跨导、最大饱和漏电流密度、电流增益截止频率分别是＋0．185／-1．22V、381．2／317．5mS／mm、275／480mA／mm、38／34GHz。增强型器件在4英寸圆片上的阈值电压标准差为19mV。     

Corrosion-induced degradation of GaAs PHEMTs under operation in high humidity conditions

We have comprehensively investigated the degradation mechanism of AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (PHEMTs) under operation in high humidity conditions. PHEMTs degradation under high humidity with bias consists of a decrease in maximum drain current (I_max) caused by a corrosion reaction at the semiconductor surface at the drain side. The decrease in I_max is markedly accelerated by the external gate-drain bias (V_dg). This originates from a reduction in the actual activation energy (E_a0) by V_dg. The degradation depends on the surface treatment prior to deposition of the SiN_x passivation film. The reduction of As-oxide at the SiN_x/semiconductor interface suppresses the corrosion reaction.     

基于GaAs PHEMT的Ku波段宽带单片中功率放大器

设计并实现了一款Ku波段宽带单片中功率放大器,依据电路原理设计了功率放大器电路,利用ADS软件对设计的电路和版图分别进行了电学参数优化与电磁仿真.放大器采用0.25 μm栅长的GaAs PHEMT作为有源器件,芯片衬底减薄至80μm,采用了NiCr金属膜电阻、重叠式MIM(金属-绝缘体-金属)电容器、空气桥连接和背面通...     

Thermal-oxide gate GaAs MOSFET's

The first thermal-oxide gate GaAs MOSFET of the deep-depletion mode is reported. The gate oxide, which has been grown by the new GaAs oxidation technique in the As2O3vapor, is so chemically stable that it can be subjected to the fabrication process. Measurement of some dc characteristics of the device fabricated has shown a strikingly suppressed hysteresis.     

Amorphous-Silicon gate GaAs FET's

Silicon-germanium-boron ternary amorphous alloy has been applied to GaAs FET as a gate contact material. A good Schottky contact with a barrier height as large as 0.94 V has been realized. Schottky-barrier gate GaAs FET's fabricated using the amorphous film as a gate contact layer exhibit excellent normally off FET characteristics of a large saturated drain curent, which has never been attained by conventional GaAs MESFET's.     

A model for hydrogen-induced piezoelectric effect in InP HEMTs and GaAs PHEMTs

We have developed a model for the impact of the hydrogen-induced piezoelectric effect on the threshold voltage of InP HEMTs and GaAs PHEMTs. We have used two-dimensional (2-D) finite element simulations to calculate the mechanical stress caused by a Ti-containing metal gate that has expanded due to hydrogen absorption. This has allowed us to map the 2-D piezoelectric charge distribution in the semiconductor heterostructure. We then used a simple electrostatics model to calculate the impact of this piezoelectric polarization charge on the threshold voltage. The model explains experimental observations of hydrogen-induced threshold voltage shifts, both in InP HEMTS and in GaAs PHEMTs. It also suggests ways to mitigate the hydrogen sensitivity of these devices.     

A GaAs gate heterojunction FET

A new semiconductor-insulator-semiconductor field-effect transistor has been fabricated. The device consists of a heavily doped n-type GaAs gate with undoped (Al,Ga)As as the gate insulator, on an undoped GaAs layer. This structure gives the device a natural threshold voltage near zero, well suited for low-voltage logic. The threshold voltage is, to first order, independent of Al mole fraction and thickness of the (Al,Ga)As layer. The layers were grown by MBE and devices fabricated using a self-aligned technique involving ion-implantation and rapid thermal annealing. A transconductance of 240 mS/mm and a field-effect mobility of about 100 000 cm²/V-s were achieved at 77 K.     

Self-aligned GaAs gate heterojunction SISFET

A self-aligned GaAs gate heterojunction enhancement-mode SISFET with a layer structure of n+-GaAs/undoped Al0.5Ga0.5As/undoped GaAs is fabricated and shows a high transconductance and a low threshold voltage. The highest transconductance at both room temperature and at 77 K ever reported on a long-channel GaAs gate SISFET, 197 mS/mm and 313 mS/mm, respectively, is obtained.     

The coherence of the gate and drain noise in stressed AlGaAs–InAlGaAs PHEMTs

Results of electrical noise measurements on stressed pseudomorphic high electron mobility transistors are reported. The DC characteristics were measured. The voltage stress between the gate and drain was carried out with the channel off and produced breakdown walkout. Different amounts of stress were applied to various devices with an unstressed control. The noise in the gate and drain currents, and the coherence between them, was measured in the range 0.1–5 kHz and analysed as white and 1/f noise. The mechanisms of the noise sources and their coherence are discussed. The coherence was found to be of a good quality or reliability indicator.     

A 630-mS/mm GaAs MESFET with Au/WSiN refractory metal gate

GaAs MESFET's with a gate length as low as 0.2 μm have been successfully fabricated with Au/WSiN refractory metal gate n⁺-self-aligned ion-implantation technology. A very thin channel layer with high carrier concentration was realized with 10-keV ion implantation of Si and rapid thermal annealing. Low-energy implantation of the n⁺-contact regions was examined to reduce substrate leakage current. The 0.2-μm gate-length devices exhibited a maximum transconductance of 630 mS/mm and an intrinsic transconductance of 920 mS/mm at a threshold voltage of -0.14 V     

Modeling of the gate junction in GaAs MESFETs

A low-signal equivalent circuit of a GaAs MESFET is suggested. In this circuit, the gate junction is represented so that a potential variation along the channel can be taken into account. A relationship between the gate current and the gate-source and drain-source voltages is found     

A new heterojunction gate GaAs FET

A new type of GaAs JFET having a heterojunction gate is proposed. The structure involves epitaxially grown layers of n-GaAs for the channel and of p-GaAlAs for the gate which can be easily delineated by the self-alignment technology using an overgrown p-GaAs. The potential advantages of the heterojunction structure for GaAs FET's over the conventional Schottky barrier are in the fewer masks for fabrication and the short channels expected. Some preliminary experimental results on fabrication technologies and dc characteristics of the new devices are described.     

GaAs基E/D PHEMT技术单片集成微波开关及其逻辑控制电路

利用GaAs基 E/D PHEMT 技术单片集成微波开关及其逻辑控制电路的制作工艺和设计方法,采用0.8μm GaAs E/D PHEMT工艺,制备出性能良好的解码器功能内置的DC~10GHz SPDT MMIC,基本实现逻辑电路与开关电路的集成. 开关电路在DC~10GHz内插入损耗小于1.6dB,隔离度大于24dB;整个电路只需要1位控制信号,有效地减少了开关电路的控制端口数目,节省了芯片面积,为GaAs多功能电路的研究奠定了基础.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Use of pt gate metallization to reduce gate leakage current in GaAs MESFETs

The use of wet-chemical removal of native oxide in a sealed nitrogen ambient prior to deposition of metal on GaAs is shown to be an effective method of engineering the Schottky barrier height of the metal contacts. Due to its higher metal work function, a barrier height of 0.98 eV for Pt on n-type GaAs is demonstrated. This is considerably higher than the barrier height of conventionally processed TiPtAu contacts (0.78 eV). MES-FETs fabricated using PtAu bilayer contacts show reverse currents an order of magnitude lower than TiPtAu contacted companion devices, higher reverse breakdown voltages and much lower gate leakage. Utilizing this technology of oxide removal and the PtAu bilayer contact provides a much simpler method of enhancing the barrier height on re-type GaAs than other techniques such as counter-doping the near-surface or inserting an interfacial layer.