A Memory‐Efficient Fingerprint Verification Algorithm Using a Multi‐Resolution Accumulator Array

Using biometrics to verify a person's identity has several advantages over the present practices of personal identification numbers (PINs) and passwords. At the same time, improvements in VLSI technology have recently led to the introduction of smart cards with 32‐bit RISC processors. To gain maximum security in verification systems using biometrics, verification as well as storage of the biometric pattern must be done in the smart card. However, because of the limited resources (processing power and memory space) of the smart card, integrating biometrics into it is still an open challenge. In this paper, we propose a fingerprint verification algorithm using a multi‐resolution accumulator array that can be executed in restricted environments such as the smart card. We first evaluate both the number of instructions executed and the memory requirement for each step of a typical fingerprint verification algorithm. We then develop a memory‐efficient algorithm for the most memory‐consuming step (alignment) using a multiresolution accumulator array. Our experimental results show that the proposed algorithm can reduce the required memory space by a factor of 40 and can be executed in real time in resource‐constrained environments without significantly degrading accuracy.     

SVM‐Based Speaker Verification System for Match‐on‐Card and Its Hardware Implementation

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32‐bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real‐time. Also, we propose a hardware design for the algorithm on a field‐programmable gate array (FPGA)‐based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA‐based solution can achieve a speed‐up of 50 times over a software‐based solution.     

Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.     

Design and extensive hardware performance analysis of an efficient pairwise key generation scheme for Smart Grid

Generating pairwise shared keys among different entities of Smart Grid is of great significance because it provides the possibility of subsequent fast and secure communications by means of symmetric key algorithms. Due to the constrained resources of the measurement devices or the smart meters, the shared key generation scheme must not only provide the security features but also put the least possible burden on the measurement devices. Several key generation schemes have been presented thus far. However, many require time and resource consuming operations, some are not suitable for hierarchical data collection in the honest‐but‐curious model, some rely on a third trusted party, and last but not least, most of them have not considered suitable hardware that can be employed for each entity of Smart Grid. Therefore, in this paper, we propose a key generation scheme that not only is free from the aforementioned issues but is also efficient in both communication and computational costs. Additionally, and more importantly, we have implemented the cryptographic elements on (a) an ARM Cortex‐M3 microcontroller, which is a proper candidate for the measurement devices; (b) an Intel Core i7‐4702MQ processor, which can be employed for either the data collectors or the power operator; and (c) 4 ARM processors, three 32‐bit and one 64‐bit. Eventually, we have evaluated the feasibility of using the ARM processors to be employed for the data collectors. We hope that the achieved results be useful for other researches in this field.     

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

A multicore system-on-chip (SoC) has been developed for various applications (recognition, inference, measurement, control, and security) that require high-performance processing and low power consumption. This SoC integrates three types of synthesizable processors: eight CPUs (M32R), two multi-bank matrix processors (MBMX), and a controller (M32C). These processors operate at 1 GHz, 500 MHz, and 500 MHz, respectively. These three types of processors are interconnected on this chip with a high-bandwidth multi-layer system bus. The eight CPUs are connected to a common pipelined bus using a cache coherence mechanism. Additionally, a 512-kB L2 cache memory is shared by the eight CPUs to reduce internal bus traffic. A multi-bank matrix processor with 2-read/1-write calculation and background I/O operation has been adopted. The 1-GHz CPU is realized using a delay management network which consists of delay monitors that can be applied for any kind of application or process technology. Our configurable heterogeneous architecture with nine CPUs and two matrix processors reduces power consumption by 45%.     

Robust smart‐card‐based remote user password authentication scheme

Smart‐card‐based remote user password authentication schemes are commonly used for providing authorized users a secure method for remotely accessing resources over insecure networks. In 2009, Xu et al. proposed a smart‐card‐based password authentication scheme. They claimed their scheme can withstand attacks when the information stored on the smart card is disclosed. Recently, Sood et al. and Song discovered that the smart‐card‐based password authentication scheme of Xu et al. is vulnerable to impersonation and internal attacks. They then proposed their respective improved schemes. However, we found that there are still flaws in their schemes: the scheme of Sood et al. does not achieve mutual authentication and the secret key in the login phase of Song's scheme is permanent and thus vulnerable to stolen‐smart‐card and off‐line guessing attacks. In this paper, we will propose an improved and efficient smart‐card‐based password authentication and key agreement scheme. According to our analysis, the proposed scheme not only maintains the original secret requirement but also achieves mutual authentication and withstands the stolen‐smart‐card attack. Copyright © 2012 John Wiley & Sons, Ltd.     

Touch‐Interactive Flexible Sustainable Energy Harvester and Self‐Powered Smart Card

Sustainable and safe energy sources combined with cost effectiveness are major goals for society when considering the current scenario of mass production of portable and Internet of Things (IoT) devices along with the huge amount of inevitable e‐waste. The conceptual design of a self‐powered “eco‐energy” smart card based on paper promotes green and clean energy, which will bring the zero e‐waste challenge one step closer to fruition. A commercial raw filter paper is modified through a fast in situ functionalization method, resulting in a conductive cellulose fiber/polyaniline composite, which is then applied as an energy harvester based on a mechano‐responsive charge transfer mechanism through a metal/conducting polymer interface. Different electrodes are studied to optimize charge transfer based on contact energy level differences. The highest power density and current density obtained from such a paper‐based “eco‐energy” smart card device are 1.75 W m^?2 and 33.5 mA m^?2 respectively. This self‐powered smart energy card is also able to light up several commercial light‐emitting diodes, power on electronic devices, and charge capacitors.     

High‐Performance Low‐Power FFT Cores

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low‐power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low‐power commutators based on an advanced interconnection, and parallel‐pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel‐pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.     

Hyperelliptic Curve Crypto‐Coprocessor over Affine and Projective Coordinates

This paper presents the design and implementation of a hyperelliptic curve cryptography (HECC) coprocessor over affine and projective coordinates, along with measurements of its performance, hardware complexity, and power consumption. We applied several design techniques, including parallelism, pipelining, and loop unrolling, in designing field arithmetic units, group operation units, and scalar multiplication units to improve the performance and power consumption. Our affine and projective coordinate‐based HECC processors execute in 0.436 ms and 0.531 ms, respectively, based on the underlying field GF(2⁸⁹). These results are about five times faster than those for previous hardware implementations and at least 13 times better in terms of area‐time products. Further results suggest that neither case is superior to the other when considering the hardware complexity and performance. The characteristics of our proposed HECC coprocessor show that it is applicable to high‐speed network applications as well as resource‐constrained environments, such as PDAs, smart cards, and so on.     

Low‐Power Design of Hardware One‐Time Password Generators for Card‐Type OTPs

Since card‐type one‐time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token‐type OTPs, it is necessary to implement power‐efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low‐power small‐area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real‐world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software‐based OTP, respectively.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

Cryptanalysis and improvement of ‘a robust smart‐card‐based remote user password authentication scheme’

With the use of smart card in user authentication mechanisms, the concept of two‐factor authentication came into existence. This was a forward move towards more secure and reliable user authentication systems. It elevated the security level by requiring a user to possess something in addition to know something. In 2010, Sood et al. and Song independently examined a smart‐card‐based authentication scheme proposed by Xu et al. They showed that in the scheme of Xu et al., an internal user of the system can turn hostile to impersonate other users of the system. Both of them also proposed schemes to improve the scheme of Xu et al. Recently, Chen et al. identified some security problems in the improved schemes proposed by Sood et al. and Song. To fix these problems, Chen et al. presented another scheme, which they claimed to provide mutual authentication and withstand lost smart card attack. Undoubtedly, in their scheme, a user can also verify the legitimacy of server, but we find that the scheme fails to resist impersonation attacks and privileged insider attack. We also show that the scheme does not provide important features such as user anonymity, confidentiality to air messages, and revocation of lost/stolen smart card. Besides, the scheme defies the very purpose of two‐factor security. Furthermore, an attacker can guess a user's password from his or her lost/stolen smart card. To meet these challenges, we propose a user authentication method with user anonymity. We show through analysis and comparison that the proposed scheme exhibits enhanced efficiency in contrast to related schemes, including the scheme of Chen et al. Copyright © 2013 John Wiley & Sons, Ltd.     

Smart WLAN Discovery for Power Saving of Dual‐Mode Terminals

Dual‐mode terminals (DMTs) equipped with cellular and WLAN interfaces have become popular in recent years. Users of DMTs can enjoy high‐speed WLAN Internet access and wide area Internet access to cellular networks. However, a DMT may consume power inefficiently when discovering a WLAN with inherently limited service coverage. In this letter, we propose to use smart WLAN discovery (SWD) to minimize the power consumption required for WLAN discovery. To minimize the power consumption of a DMT, an SWD DMT activates its WLAN interface only when the DMT transfers data within the WLAN coverage area. The simulation results of SWD show an improved power‐saving performance compared to previous WLAN discovery schemes.     

On‐Chip Bus Serialization Method for Low‐Power Communications

One of the critical issues in on‐chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low‐power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word‐to‐word and bit‐by‐bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG‐4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost‐effective when implemented as a hardware circuit since its algorithm is very simple.     

New Thermal‐Aware Voltage Island Formation for 3D Many‐Core Processors

The power consumption of 3D many‐core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on‐chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per‐core VI design. We propose a 3D many‐core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on‐chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many‐core processors.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

Flexible Prime‐Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy‐efficient (low power) prime‐field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 μm standard CMOS technology, performs an 81‐bit divisor multiplication in 503 ms consuming only 6.55 μJ of energy (average power consumption is 12.76 μW). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.     

Improvement of robust smart‐card‐based password authentication scheme

Smart‐card‐based password authentication scheme is one of the commonly used mechanisms to prevent unauthorized service and resource access and to remove the potential security threats over the insecure networks and has been investigated extensively in the last decade. Recently, Chen et al. proposed a smart‐card‐based password authentication scheme and claimed that the scheme can withstand offline password guessing attacks even if the information stored in the smart card is extracted by the adversary. However, we observe that the scheme of Chen et al. is insecure against offline password guessing attacks in this case. To remedy this security problem, we propose an improved authentication protocol, which inherits the merits of the scheme of Chen et al. and is free from the security flaw of their scheme. Compared with the previous schemes, our improved scheme provides more security guarantees while keeping efficiency. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.     

Cryptographic identification methods for smart cards in the processof standardization

Identification using integrated-circuit cards in credit card format with a built-in microcontroller (smart cards) is examined. The process by which the terminal's card adapter device verifies the authenticity of the smart card, called cryptographic node authentication, is examined. The methods used for node authentication, all of which are based on interrogation protocols, can be divided into the following categories on the basis of their fundamental cryptographic principles: challenge response with symmetrical key algorithms; challenge response with trapdoor public key algorithms; and zero-knowledge-based protocols. The various methods are described and compared, and the outlook for standardization is assessed