A Novel Mobile Antenna for Ku‐Band Satellite Communications

A mobile antenna for multimedia communications with Ku‐band geostationary satellite KOREASAT‐3 and JSAT‐2A is presented. The forward link of the satellite communication is 11.7 to 12.75 GHz, and the return link is 14.0 to 14.5 GHz. The mobile antenna is designed to be a stair structure using 24 active phased array elements in order to provide a low profile, and to be at a non‐periodic array distance using the genetic algorithm. Also, the designed antenna uses the double beam forming method for stable satellite tracking. The fabricated mobile antenna is examined using various experiments to confirm its capability for practical application. From the measured results, the fabricated mobile antenna system is confirmed to have a good performance.     

A Full-360° Reflection-Type Phase Shifter With Constant Insertion Loss

A new reflection-type phase shifter with a full 360deg relative phase shift range and constant insertion loss is presented. This feature is obtained by incorporating a new cascaded connection of varactors into the impedance-transforming quadrature coupler. The required reactance variation of a varactor can be reduced by controlling the impedance ratio of the quadrature coupler. The implemented phase shifter achieves a measured maximal relative phase shift of 407deg, an averaged insertion loss of 4.4 dB and return losses better than 19 dB at 2 GHz. The insertion-loss variation is within plusmn0.1 and plusmn0.2 dB over the 360deg and 407deg relative phase shift tuning range, respectively.     

A New 90° Constant Phase Shifter for the VHF Band

This concise paper presents the realization of a 90°constant phase shifter in the VHF band, which is entirely different from the conventional method for the realization of constant phase shifters in the audio frequency range. The construction of the 90° constant phase shifter is simple and can be easily realized by using a transmission line, and the lumped constant elements, R, L, C. Experimental verification is included.     

Modified rain attenuation model for tropical regions for Ku‐Band signals

Attenuation measurement on Ku‐ band satellite signal in a tropical site, Fiji is presented. Rain‐attenuation prediction by ITU‐R and the Crane Global models showed noticeable deviation to the measured values. Unlike the monotonic decrease predicted by these models, exceedance of rain‐rate and attenuation in Fiji and other tropical regions showed the presence of breakpoints. For Suva, the breakpoint in rain‐rate and attenuation were at 58 mm/h and 9.4 dB with exceedances of 0.009 and 0.018%, respectively. Modifications to the ITU‐R model are proposed in this paper, for adopting it in the tropics. These modifications are based on the properties that in the tropics (i) the accumulation time factor at the breakpoints is an invariant (ii) for elevation angles <60° and at high rain rates multiple rain cells intersect the slant path. The attenuation exceedance is predicted by two expressions similar to the ITU‐R model, one for rain‐rates lower than the breakpoint rain‐rate and the other above it. The modified prediction model show remarkable agreement with the measured Ku‐band attenuation in seven tropical sites. Copyright © 2006 John Wiley & Sons, Ltd.     

X‐Band Phased Array Antenna Using Ferroelectric (Ba,Sr)TiO3 Coplanar Waveguide Phase Shifter

A phased array antenna was fabricated using four‐element ferroelectric phase shifters with a coplanar waveguide (CPW) transmission line structure based on a Ba0.6Sr0.4TiO3(BST)/MgO structure. Epitaxial BST films were deposited on MgO (001) substrates by pulsed laser deposition. To attain the large differential phase shift and small losses for a ferroelectric CPW phase shifter, an impedance‐matching‐part adding technique between the effective transmission line and connecting cable was used. The return loss and insertion loss for this technique‐adapted BST CPW device were improved with respect to those for a normal BST CPW device. For an X‐band phased array antenna system consisting of ferroelectric BST CPW phase shifters, power divider, dc block, patch antenna, and programmed dc power, the steering beam could be tilted by 15° in either direction.     

A Low Power 16‐Bit RISC Microprocessor Using ECRL Circuits

This paper presents a low power 16‐bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a 0.35 µm CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four‐phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non‐adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.     

A Broadband Digital Step Attenuator with Low Phase Error and Low Insertion Loss in 0.18‐μm SOI CMOS Technology

This paper presents a 5‐bit digital step attenuator (DSA) using a commercial 0.18‐μm silicon‐on‐insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T‐type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is , including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC‐to‐20‐GHz SOI DSA.     

应用于DBS移动接收中的5位数字移相器——低成本、Ku波段

提出了一种应用于DBS移动接收中的5位数字移相器的设计方案,并通过实验验证了其实际性能。该移相器采用加载线型和反射型移相原理,首先应用ADS软件进行设计仿真;仿真结果显示该移相器具有频带内高移相精度、低插入损耗和低VSWR等性能,符合设计要求。最后使用Agilent矢量网络分析仪对实物进行测试,进而验证了设计方案的正确性。     

16‐QAM OFDM‐Based K‐Band LoS MIMO Communication System with Alignment Mismatch Compensation

This paper presents a novel K‐band (18 GHz) 16‐quadrature amplitude modulation (16‐QAM) orthogonal frequency‐division multiplexing (OFDM)‐based 2 × 2 line‐of‐sight multi‐input multi‐output communication system. The system can deliver 356 Mbps on a 56 MHz channel. Alignment mismatches, such as amplitude and/or phase mismatches, between the transmitter and receiver antennas were examined through hardware experiments. Hardware experimental results revealed that amplitude mismatch is related to antenna size, antenna beam width, and link distance. The proposed system employs an alignment mismatch compensation method. The open‐loop architecture of the proposed compensation method is simple and enables facile construction of communication systems. In a digital modem, 16‐QAM OFDM with a 512‐point fast Fourier transform and (255, 239) Reed‐Solomon forward error correction codecs is used. Experimental results show that a bit error rate of 10^?5 is achieved at a signal‐to‐noise ratio of approximately 18.0 dB.     

10‐Bit 200‐MS/s Current‐Steering DAC Using Data‐Dependant Current‐Cell Clock‐Gating

This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with V_DD=1.2 V. Its area is 0.21 mm². It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively.     

NbF5: A Novel α‐Phase Stabilizer for FA‐Based Perovskite Solar Cells with High Efficiency

The HC(NH₂)₂⁺(FA⁺) is a well‐known substitute to CH₃NH₃⁺(MA⁺) for its capability to extend light utilization for improved power conversion efficiency for perovskite solar cells; unfortunately, the dark cubic phase (α‐phase) can easily transition to the yellow orthorhombic phase (δ‐phase) at room temperature, an issue that prevents its commercial application. In this report, an inorganic material (NbF₅) is developed to stabilize the desired α‐phase perovskite material by incorporating NbF₅ additive into the perovskite films. It is found that the NbF₅ additive effectively suppresses the formation of the yellow δ‐phase in the perovskite synthesis and aging process, thus enhancing the humidity and light‐soaking stability of the perovskite film. As a result, the perovskite solar cells with the NbF₅ additive exhibit improved air stability by tenfold, retaining nearly 80% of their initial efficiency after aging in air for 50 d. In addition, under full‐sun AM 1.5 G illumination of a xenon lamp without any UV‐reduction, the perovskite solar cells with the NbF₅ additive also show fivefold improved illumination stability than the control devices without NbF₅.     

A Platform‐Based SoC Design of a 32‐Bit Smart Card

In this paper, we describe the development of a platform‐based SoC of a 32‐bit smart card. The smart card uses a 32‐bit microprocessor for high performance and two cryptographic processors for high security. It supports both contact and contactless interfaces, which comply with ISO/IEC 7816 and 14496 Type B. It has a Java Card OS to support multiple applications. We modeled smart card readers with a foreign language interface for efficient verification of the smart card SoC. The SoC was implemented using 0.25 µm technology. To reduce the power consumption of the smart card SoC, we applied power optimization techniques, including clock gating. Experimental results show that the power consumption of the RSA and ECC cryptographic processors can be reduced by 32% and 62%, respectively, without increasing the area.     

A 0.13-μ m CMOS Phase Shifter Using Tunable Positive/Negative Refractive Index Transmission Lines

This letter presents a tunable positive/negative refractive index transmission line (TL) phase shifter utilizing active circuits. It comprises a microstrip TL loaded with series varactors and a shunt monolithic microwave integrated circuit (MMIC) to synthesize a tunable inductor. This implementation increases the phase tuning range and maintains the input and output matching of the phase shifter across the entire phase tuning range, while eliminating the need for bulky passive inductors. The phase shifter is capable of providing both positive and negative phase shifts. The MMIC tunable inductors are fabricated in a 0.13-mum CMOS process and operate from a 1.5-V supply. The phase shifter achieves a phase of -40deg to +34deg at 2.5GHz from a single stage with less than -19dB return loss, and better than 1.1-dB insertion loss at 2.5 GHz. The phase shifter has a 1-GHz bandwidth over which the return loss remains better than 12.1dB     

E‐Band Wideband MMIC Receiver Using 0.1 µm GaAs pHEMT Process

In this paper, the implementations of a 0.1 µm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single‐chip receiver for 70/80 GHz point‐to‐point communications are presented. To obtain high‐gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five‐stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five‐stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of –1.5 dBm to 1.5 dBm. Finally, a single‐chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of –21 dBm.     

Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

A Low‐Spur CMOS PLL Using Differential Compensation Scheme

This paper proposes LC voltage‐controlled oscillator (VCO) phase‐locked loop (PLL) and ring‐VCO PLL topologies with low‐phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer‐resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out‐band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65‐nm or 45‐nm process. The measured results of the LC‐VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring‐VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.     

A Radiometric Method for Measuring the Insertion Loss of Radome Materials

Though radomes have been used for years as a means of protecting antennas from the elements, little appears in the Iiterature to aid the engineer in his choice of the radome material to use in a particular installation. This may be due to the fact that many radome materials are adequate when used with a receiving system having a mixer (i.e., relatively hot) front end. However, an improper choice of radome material can seriously degrade a receiving system that employs a maser or other low-noise front end. A radiometric technique for the measurement of insertion loss is described, and a sample calculation, including error analysis, is presented.     

A Ka‐Band 6‐W High Power MMIC Amplifier with High Linearity for VSAT Applications

A Ka‐band 6‐W high power microwave monolithic integrated circuit amplifier for use in a very small aperture terminal system requiring high linearity is designed and fabricated using commercial 0.15‐μm GaAs pHEMT technology. This three‐stage amplifier, with a chip size of 22.1 mm² can achieve a saturated output power of 6 W with a 21% power‐added efficiency and 15‐dB small signal gain over a frequency range of 28.5 GHz to 30.5 GHz. To obtain high linearity, the amplifier employs a class‐A bias and demonstrates an output third‐order intercept point of greater than 43.5 dBm over the above‐mentioned frequency range.     

Binary Power Amplifier with 2‐Bit Sigma‐Delta Modulation Method for EER Transmitter

A novel power amplifier for a polar transmitter is proposed to achieve better spectral performance for a wideband envelope signal. In the proposed scheme, 2‐bit sigma‐delta (ΣΔ) modulation of the envelope signal is introduced, and the power amplifier configuration is modified in a binary form to accommodate the 2‐bit digitized envelope signals. The 2‐bit ΣΔ modulator lowers the noise of the envelope signal by fine quantization and thus enhances the spectral property of the RF signal. The Ptolemy simulation results of the proposed structure show that the spectral noise is reduced by 10 dB in a full transmit band of the EDGE system. The dynamic range is also enhanced. Since the performance is improved without increasing the over‐sampling ratio, this technique is best suited for wireless communication with high data rates.