Digital Audio Effect System‐on‐a‐Chip Based on Embedded DSP Core

This paper describes the implementation of a digital audio effect system‐on‐a‐chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co‐design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 μm CMOS process and evaluated successfully on a real‐time test board.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

A New Multi‐site Test for System‐on‐Chip Using Multi‐site Star Test Architecture

As the system‐on‐chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.     

A Tumor‐on‐a‐Chip System with Bioprinted Blood and Lymphatic Vessel Pair

Current in vitro antitumor drug screening strategies insufficiently mimic biological systems. They tend to lack true perfusion and draining microcirculation systems, which may post significant limitations in explicitly reproducing the transport kinetics of cancer therapeutics. Herein, the fabrication of an improved tumor model consisting of a bioprinted hollow blood vessel and a lymphatic vessel pair, hosted in a 3D tumor microenvironment‐mimetic hydrogel matrix is reported, termed as the tumor‐on‐a‐chip with a bioprinted blood and a lymphatic vessel pair (TOC‐BBL). The bioprinted blood vessel is a perfusable channel with an opening on both ends, while the bioprinted lymphatic vessel is blinded on one end, both of which are embedded in a hydrogel tumor mass, with vessel permeability individually tunable through optimization of the compositions of the bioinks. It is demonstrated that systems with different combinations of these bioprinted blood/lymphatic vessels exhibit varying levels of diffusion profiles for biomolecules and anticancer drugs. The results suggest that this unique in vitro tumor model containing the bioprinted blood/lymphatic vessel pair may have the capacity of simulating the complex transport mechanisms of certain pharmaceutical compounds inside the tumor microenvironment, potentially providing improved accuracy in future cancer drug screening.     

Long‐Term Electrical and Mechanical Function Monitoring of a Human‐on‐a‐Chip System

The goal of human‐on‐a‐chip systems is to capture multiorgan complexity and predict the human response to compounds within physiologically relevant platforms. The generation and characterization of such systems is currently a focal point of research given the long‐standing inadequacies of conventional techniques for predicting human outcome. Functional systems can measure and quantify key cellular mechanisms that correlate with the physiological status of a tissue, and can be used to evaluate therapeutic challenges utilizing many of the same endpoints used in animal experiments or clinical trials. Culturing multiple organ compartments in a platform creates a more physiologic environment (organ–organ communication). Here is reported a human 4‐organ system composed of heart, liver, skeletal muscle, and nervous system modules that maintains cellular viability and function over 28 days in serum‐free conditions using a pumpless system. The integration of noninvasive electrical evaluation of neurons and cardiac cells and mechanical determination of cardiac and skeletal muscle contraction allows the monitoring of cellular function, especially for chronic toxicity studies in vitro. The 28‐day period is the minimum timeframe for animal studies to evaluate repeat dose toxicity. This technology can be a relevant alternative to animal testing by monitoring multiorgan function upon long‐term chemical exposure.     

Nonmulberry Silk Based Ink for Fabricating Mechanically Robust Cardiac Patches and Endothelialized Myocardium‐on‐a‐Chip Application

Bioprinting holds great promise toward engineering functional cardiac tissue constructs for regenerative medicine and as drug test models. However, it is highly limited by the choice of inks that require maintaining a balance between the structure and functional properties associated with the cardiac tissue. In this regard, a novel and mechanically robust biomaterial‐ink based on nonmulberry silk fibroin protein is developed. The silk‐based ink demonstrates suitable mechanical properties required in terms of elasticity and stiffness (≈40 kPa) for developing clinically relevant cardiac tissue constructs. The ink allows the fabrication of stable anisotropic scaffolds using a dual crosslinking method, which are able to support formation of aligned sarcomeres, high expression of gap junction proteins as connexin‐43, and maintain synchronously beating of cardiomyocytes. The printed constructs are found to be nonimmunogenic in vitro and in vivo. Furthermore, delving into an innovative method for fabricating a vascularized myocardial tissue‐on‐a‐chip, the silk‐based ink is used as supporting hydrogel for encapsulating human induced pluripotent stem cell derived cardiac spheroids (hiPSC‐CSs) and creating perfusable vascularized channels via an embedded bioprinting technique. The ability is confirmed of silk‐based supporting hydrogel toward maturation and viability of hiPSC‐CSs and endothelial cells, and for applications in evaluating drug toxicity.     

Dynamic Fluoroalkyl Polyethylene Glycol Co‐Polymers: A New Strategy for Reducing Protein Adhesion in Lab‐on‐a‐Chip Devices

Non‐specific adsorption of biomolecules (or “biofouling”) is a major problem in microfluidics and many other applications. The problem is particularly pernicious in digital microfluidics (DMF, a technique in which droplets are manipulated electrodynamically on an array of electrodes coated with a hydrophobic insulator), as local increases in surface energy that arise from fouling can cause droplet movement to fail. We report a new solution to this problem: a device coating bearing a combination of fluorinated poly(ethylene glycol) functionalities (FPEG) and perfluorinated methacrylate (FA) moieties. A range of different FPEG‐FA copolymers were synthesized containing varying amounts of FPEG relative to the fluorinated backbone. Coatings with low%FPEG were found to result in significant reductions in protein adsorption and improvements in device lifetime (up to 5.5‐fold) relative to the state of the art. An analysis of surface topology and chemistry suggests that FPEG‐FA surfaces undergo a dynamic reconstruction upon activation by applying DMF driving potentials, with FPEG groups forming vertical protrusions out of the plane of the device surface. An analysis of changes in surface wettability and adhesion as a function of activation supports this hypothesis. This innovation represents an advance for digital microfluidics, and may also find use in other applications that are currently limited by biofouling.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

Verification Platform with ARM‐ and DSP‐Based Multiprocessor Architecture for DVB‐T Baseband Receivers

In this paper, we introduce a new verification platform with ARM‐ and DSP‐based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB‐T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co‐verification tool. We present a dual‐processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB‐T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB‐T.     

New Path‐Setup Method for Optical Network‐on‐Chip

With high bandwidth, low interference, and low power consumption, optical network‐on‐chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path‐setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non‐blocking optical router is designed to support the new method. The simulation results show the new path‐setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot‐I, and hotspot‐II traffic patterns, respectively. The end‐to‐end delay performance is also improved.     

AE32000B: a Fully Synthesizable 32‐Bit Embedded Microprocessor Core

In this paper, we introduce a fully synthesizable 32‐bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35‐·m library and a 0.18‐·m library. With the 0.35‐·m library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18‐·m library.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

A Bluetooth Based Sensor Network for Civil Infrastructure Health Monitoring

Communicating with sensors has long been limited either to wired connections or to proprietary wireless communication protocols. Using a ubiquitous and inexpensive wireless communication technology to create Sensor Area Networks (SANs) will accelerate the extensive deployment of sensor technology. Bluetooth, an emerging, worldwide standard for inexpensive, local wireless communication is a viable choice for SANs because of its inherent support for some of the important requirements – low power, small form factor, low cost and sufficient communication range. In this paper we outline an approach, centered on the Bluetooth technology, to support a sensor network composed of fixed wireless sensors for health monitoring of highways, bridges and other civil infrastructures. We present a topology formation scheme that not only takes into account the traffic generated by different sensors but also the associated link strengths, buffer capacities and energy availability. The algorithm makes no particular assumptions as to the placement of nodes, and not all nodes need to be in radio proximity of each other. The output is a tree shaped scatternet rooted at the sensor hub (data logger) that is balanced in terms of traffic carried on each of the links. We also analyze the scheduling, routing and healing aspects of the resulting sensor-net topology.     

Lead‐free on‐laminate laser soldering: a new module assembling concept

We demonstrate lead‐free laser soldering of standard industrial solar cells. The laser‐soldered contacts stay stable for more than 240 accelerated ageing cycles by humidity–freeze test and withstand peel forces in excess of 10 N/cm. Laser soldering is demonstrated while the cells are lying on the ethylene vinyl acetate (EVA) foil. This permits to connect the solar cells to the lead‐free tinned copper ribbons directly on the lamination materials. We also demonstrate soldering on the bottom side by lasering through the glass and the non‐polymerized EVA. With the aid of a pick and place robot it thus becomes possible to avoid all string handling. On‐laminate laser soldering (OLLS) technique, which permits a high level of automation and process control, induces little thermal and mechanical stress, reduces the handling and should thus be of particular advantage for assembling modules with very thin cells at a high yield. Copyright © 2007 John Wiley & Sons, Ltd.     

Fabrication of Stable Metallic Patterns Embedded in Poly(dimethylsiloxane) and Model Applications in Non‐Planar Electronic and Lab‐on‐a‐Chip Device Patterning

This article describes the fabrication of durable metallic patterns that are embedded in poly(dimethylsiloxane) (PDMS) and demonstrates their use in several representative applications. The method involves the transfer and subsequent embedding of micrometer‐scale gold (and other thin‐film material) patterns into PDMS via adhesion chemistries mediated by silane coupling agents. We demonstrate the process as a suitable method for patterning stable functional metallization structures on PDMS, ones with limiting feature sizes less than 5 μm, and their subsequent utilization as structures suitable for use in applications ranging from soft‐lithographic patterning, non‐planar electronics, and microfluidic (lab‐on‐a‐chip, LOC) analytical systems. We demonstrate specifically that metal patterns embedded in both planar and spherically curved PDMS substrates can be used as compliant contact photomasks for conventional photolithographic processes. The non‐planar photomask fabricated with this technique has the same surface shape as the substrate, and thus facilitates the registration of structures in multilevel devices. This quality was specifically tested in a model demonstration in which an array of one hundred metal oxide semiconductor field‐effect transistor (MOSFET) devices was fabricated on a spherically curved Si single‐crystalline lens. The most significant opportunities for the processes reported here, however, appear to reside in applications in analytical chemistry that exploit devices fabricated using the methods of soft lithography. Toward this end, we demonstrate durably bonded metal patterns on PDMS that are appropriate for use in microfluidic, microanalytical, and microelectromechanical systems. We describe a multilayer metal‐electrode fabrication scheme (multilaminate metal–insulator–metal (MIM) structures that substantially enhance performance and stability) and use it to enable the construction of PDMS LOC devices using electrochemical detection. A polymer‐based microelectrochemical analytical system, one incorporating an electrode array for cyclic voltammetry and a microfluidic system for the electrophoretic separation of dopamine and catechol with amperometric detection, is demonstrated.