Hardware Elliptic Curve Cryptographic Processor Over$rm GF(p)$

A novel hardware architecture for elliptic curve cryptography (ECC) over$ GF(p)$is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications.     

一种新型快速有限域乘法器设计实现

介绍一种新型有限域乘法器,其基本原理是引入多项式拆分概念和多项式拆分方法,将m次的多项式拆分成两个m/2次多项式分别做有限域乘法,这样可以降低乘法运算的阶数,用加法计算电路来代替。并且根据这种算法设计了新型乘法器的电路实现,将这种新型乘法器并且与比特串行乘法器的仿真结果做对比。结果表明新型的有限域乘法器达到了较高的系统数据吞吐率,可以应用于纠错系统、RS编码器和译码器中。     

Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit‐parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application‐specific integrated circuit and field‐programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.     

Compact implementations of Curve Ed448 on low‐end IoT platforms

Elliptic curve cryptography is a relatively lightweight public‐key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low‐end IoT processors (ie, 8‐bit AVR and 16‐bit MSP processors). In particular, the three‐level and two‐level subtractive Karatsuba algorithms are adopted for multi‐precision multiplication on AVR and MSP processors, respectively, and two‐level Karatsuba routines are employed for multi‐precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat‐based inversion operations are used to mitigate side‐channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.     

可重构点乘运算的FPGA设计

文章在深入分析ECC点乘运算的FPGA实现的基础上,提出了一种参数可重构的、基于正规基有限域运算的ECC点乘运算结构。该点乘运算结构采用了复用、并行化等措施,在FPGA上实现了GF（2^191）的ECC点乘运算。在Altera FPGA上的仿真结果表明：在50Mhz时钟下,一次点乘运算只需413．28us。     

Customizable elliptic curve cryptosystems

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2/sup m/), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.     

基于脉动阵列结构的多项式基乘法器的设计

提出了一类基于脉动阵列结构的字串行有限域乘法器架构。架构基于多项式基,支持m相似文献   

基于比特重组快速模约简的高面积效率椭圆曲线标量乘法器设计

针对现有椭圆曲线密码标量乘法器难以兼顾灵活性和面积效率的问题,该文设计了一种基于比特重组快速模约简的高面积效率标量乘法器。首先,根据椭圆曲线标量乘的运算特点,设计了一种可实现乘法和模逆两种运算的硬件复用运算单元以提高硬件资源使用率,并采用Karatsuba-Ofman算法提高计算性能。其次,设计了基于比特重组的快速模约简算法,并实现了支持secp256k1, secp256r1和SCA-256(SM2标准推荐曲线)快速模约简计算的硬件架构。最后,对点加和倍点的模运算操作调度进行了优化,提高乘法与快速模约简的利用率,降低了标量乘计算所需的周期数量。所设计的标量乘法器在55 nm CMOS工艺下需要275 k个等效门,标量乘运算速度为48309次/s,面积时间积达到5.7。     

FPGA内RS编码器的3种算法实现

RS码是一种纠错能力强、使用广泛的多进制循环码。首先介绍了RS编码器原理、有限域乘法器的实现方法以及设计实现的一般框图,然后以RS(204,188,8)码为例,给出了采用一般乘法器、常数乘法器和常数加法器的RS编码器的算法实现原理,并基于现场可编程门阵列FPGA给出了实现方法,根据设计实现的结果,分析了算法的优劣,最后得到了较优的设计方法。     

一种改进控制逻辑的面积优化高速RS解码器

给出了一个完整的基于时域解码算法的Reed-Solomon解码器流水结构，用来计算错误位置多项式和错误估值多项式的改进欧几里德算法（Modified Euclid Algorthn,MEA）模块，通过寄存器分组并行计算，大大提高了处理速度。同时，该设计优化了MEA模块的控制逻辑，避免了寄存器组之间的物理交换，每一次迭代均可在固定的时钟周期内完成。此外，对解码器中16个有限域常数乘法器进行了特别的门数优化，求错误值部分采用高效的比特并行求逆电路。该解码器适用于HDTV等数字视频系统。     

面向全同态加密的有限域FFT算法FPGA设计

大数乘法是全同态加密算法中一个不可或缺的单元模块,也是其中耗时最多的模块,设计一个性能优良的大数乘法器有助于推进全同态加密的实用化进程。针对SSA大数乘法器的实现需求,该文采用可综合Verilog HDL语言完成了一个1624 bit有限域FFT算法的FPGA设计,通过构建树型大数求和单元和并行化处理方法有效提高了FFT算法的速度。与VIM编译环境下的系统级仿真结果比较,验证了有限域FFT算法FPGA设计的正确性。     

基于有符号数字系统的Montgomery模逆算法及其硬件实现

 在椭圆曲线密码中,模逆运算是有限域运算中最复杂、最耗时且硬件实现难度最大的运算.本文在Kaliski算法的基础上,提出了基于有符号数字系统的Montgomery模逆算法,它支持素数域和二进制域上任意多精度参数的求模逆运算.据此算法,设计了相应的硬件结构方案,并给出了面积复杂度和时间复杂度分析.仿真结果表明,相比于其它模逆算法硬件设计方案,本文提出的基于有符号数字系统的Montgomery模逆算法在运算速度、电路面积、灵活性等方面具有显著的优越性.     

A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit

A submicron CMOS 1-Mb RAM with a built-in error checking and correcting (ECC) circuit is described. An advanced bidirectional parity code with a self-checking function is proposed to reduce the soft error rate. A distributed sense circuit makes it possible to implement a small memory cell size of 20 /spl mu/m/SUP 2/ in combination with a trench capacitor technique. The 1M word/spl times/1 bit device was fabricated on a 6.4/spl times/8.2 mm chip. The additional 98-kb parity cells and the built-in ECC circuit occupy about 12% of the whole chip area. The measured access time is 140 ns, including 20 ns ECC operation.     

用EMODL实现的高速低功耗流水线乘法器

实现快速、低功耗以及节省面积的乘法器对高性能微处理器 (例如 DSP和 RISC)而言是至关重要的。文中详尽论述了新型的增强型多输出多米诺逻辑 ( EMODL)及其 n-MOS赋值树的尺寸优化方法 ,并用它实现了高速低功耗 2 0× 2 0 bit流水线乘法器。最后 ,通过 HSPICE仿真 ,确认了该乘法器结构的优越性 :流水线等待时间小 ( 2倍于系统时钟 )、运算速度高 ( 10 0 MOPS)以及低功耗 ( 2 3 .94m W)     

一类有限域乘法器的设计实现

提出了一种基于有限域内移位三项式基及其弱共轭基的比特并行乘法器的新结构.在由三项式生成的域内,此种结构的比特并行乘法器易于设计者使用硬件描述语言实现.采用Encounter软件对该结构进行布局布线后,发现其面积与关键路径时延都达到了设计目标的要求,在设计性能和硬件约束条件上取得了比较好的平衡.     

An area-efficient bit-serial integer and GF(2) multiplier

This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers as well as for multiplication in finite fields of order 2ⁿ. It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [M. Kunde, H.W. Lang, M. Schimmler, H. Schmeck, H. Schröder, Parallel Computing 7 (1988) 25-39, H.W. Lang, Integration, the VLSI Journal 4 (1986) 65-74]. The multiplier operates least significant bit (LSB)-first for integer multiplication and most significant bit ( )-first for finite field multiplication. It is a modular bit-serial design, which on the one hand can be efficiently implemented in hardware and on the other hand has the advantage that it can handle operands of arbitrary length.     

基于GF(2~m)的椭圆曲线求逆算法的改进研究

针对二进制域上现有求逆算法计算量大、并行度小、速度慢的缺点进行改进,基于二元Euclidean算法提出了改进,设计了相应的乘法器硬件结构,并且分析了其运算效能和资源占用情况。将此求逆计算器的并行改进算法使用Verilog语言编程实现,利用Xilinx ISE 12.4对整个求逆算法综合仿真(行为级),在Xilinx Virtex-5 XC5VFX70T的硬件平台上验证求逆算法的运算效率,结果表明对求逆算法的改进有效地提高了求逆运算的速度。     

一种用于ECC密码体制的模乘器设计

提出了一种基于Montgomery算法的模乘器。与现有结构相比,由于采用了多级流水线的乘法器结构,提高了系统的时钟频率;并通过引入预计算单元,解决了流水线停顿的问题,提高了系统的并行性,减少了所需的时钟数。该模乘器位长233位,基于SMIC 0.18μm最坏工艺的综合结果表明,电路的关键路径最大时延为3.8 ns,芯片面积2 mm2。一次模乘计算只需要108个时钟周期,适合ECC密码体制的应用要求。     

基于XTR体制的盲签名方案

XTR是一种新的基于有限域的乘法群的子群中元素迹的紧致表示的公钥密码体制。与RSA和ECC相比较,同等安全程度下 XTR密钥长度远远小于 RSA,最多只是 ECC密钥长度的 2倍,但XTR参数和密钥选取的速度远远快于 ECC。利用基于离散对数问题的盲签名方案以及有限域中元素迹的快速算法,该文给出了两种基于 XTR体制的盲签名方案,其安全性等价于解 XTR-DL困难问题,但是传输的数据量只有原来方案的 1/3。     

基于FPGA技术的GF(2m)域乘法器的研究和设计

椭圆曲线密码体制以其密钥短、安全强度高的优点获得了广泛的重视和应用,而GF(2m)有限域乘法运算是该密码体制最主要的运算.本文研究了基于FPGA芯片的多项式基乘法器的快速设计方法,并给出了面积与速度的比较和分析.