单芯片大功率RFLDMOS晶体管设计与实验

传统射频LDMOS晶体管的源区采用重掺杂p+sinker结构,该结构会占据较大的芯片面积。文中采用槽型sinker结构,可将源区sinker面积减少1/3以上。通过流片实验,得到饱和电流为170 mA/mm、击穿电压120 V、截止频率和最大振荡频率分别为5.5 GHz和10 GHz的RF LDMOS器件。在50 V工作电压、1 090 MHz频点下栅宽345 mm单芯片器件的最大输出功率362 W,功率增益15.6 dB,漏极效率38.1%。     

Performance comparison of substrate coupling effect between silicon and SOI substrates in RF-CMOS technology

Substrate coupling may severely degrade the electrical performances of high-speed and RF integrated circuits. An isolation technique study of parasitic effects due to substrate coupling between two blocks of integrated circuits in an RF CMOS 90 nm technology is presented. Isolation performances are compared for both bulk silicon (Si) and silicon-on-insulator (SOI) substrate. For every substrate, a compact electrical model matching well with measurement results is proposed for test structures composed of 50times50 mum cells surrounded with an appropriate guard ring. An isolation improvement of 10 dB is reached by an additional P-type guard ring placed around one cell and an isolation level of 45 dB is achieved at 1 GHz for bulk Si substrate     

6‐GHz‐to‐18‐GHz AlGaN/GaN Cascaded Nonuniform Distributed Power Amplifier MMIC Using Load Modulation of Increased Series Gate Capacitance

A 6‐GHz‐to‐18‐GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a 0.25‐μm AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power‐added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse‐mode condition of a 100‐μs pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.     

A Single Transistor‐Level Direct‐Conversion Mixer for Low‐Voltage Low‐Power Multi‐band Radios

A CMOS direct‐conversion mixer with a single transistor‐level topology is proposed in this paper. Since the single transistor‐level topology needs smaller supply voltage than the conventional Gilbert‐cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system‐on‐a‐chip (SoC). The proposed direct‐conversion mixer is designed for the multi‐band ultra‐wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and ?10 dBm, respectively, with multi‐band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.     

W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

A Subthreshold CMOS RF Front‐End Design for Low‐Power Band‐III T‐DMB/DAB Receivers

This letter presents a CMOS RF front‐end operating in a subthreshold region for low‐power Band‐III mobile TV applications. The performance and feasibility of the RF front‐end are verified by integrating with a low‐IF RF tuner fabricated in a 0.13‐μm CMOS technology. The RF front‐end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front‐end is 13.8 mW from a 1.2 V supply.     

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P⁺ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S₂₁| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.     

2.4‐GHz Power Amplifier with Power Detector Using Metamaterial‐Based Transformer‐Type On‐Chip Directional Coupler

This letter presents a power amplifier (PA) with an on‐chip power detector for 2.4‐GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial‐based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.     

Small‐Size and High‐Isolation MIMO Antenna for WLAN

A small‐sized (15 mm×30 mm) planar monopole MIMO antenna that offers high‐isolation performance is presented in this letter. The antenna is miniaturized using inductive coupling within a meander‐line radiator and capacitive coupling between a radiator and an isolator. High isolation is achieved by a T‐shaped stub attached to the ground plane between two radiators, which also contributes to the small size using a folded structure and the capacitive coupling with radiators. The proposed antenna operates for the WLAN band within 2.4 GHz to 2.483 GHz. The measured isolation (S₂₁) is about –30 dB, and the envelope correlation coefficient is less than 0.1.     

Substrate noise coupling through planar spiral inductor

While precious studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radiofrequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise source is less than -30 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tuned-gain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using a broken guard ring in reducing inductor induced substrate noise is also examined     

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a$hboxp^+ $/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18$muhbox m$3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring.     

A D‐Band Balanced Subharmonically‐Pumped Resistive Mixer Based on 100‐nm mHEMT Technology

A D‐band subharmonically‐pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a 180° power divider structure consisting of a Lange coupler followed by a λ/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs‐based metamorphic high electron mobility transistor process with 100‐nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4‐dBm LO drive and an intermediate frequency of 100 MHz. The input 1‐dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.     

A Novel 94-GHz MHEMT Resistive Mixer Using a Micromachined Ring Coupler

In this letter, we present a high performance 94-GHz millimeter-wave monolithic integrated circuit resistive mixer using a 70-nm metamorphic high electron mobility transistor (MHEMT) and micromachined ring coupler. A novel three-dimensional structure of a resistive mixer was proposed in this work, and the ring coupler with the surface micromachined dielectric-supported air-gap microstrip line structure was used for high local oscillator/radio frequency (LO–RF) isolation. Also, the LO–RF isolation was optimized through the simulation. The fabricated mixer has excellent LO–RF isolation, greater than 29 dB, in 2-GHz bandwidth of 93–95GHz. The good conversion loss of 8.9dB was measured at 94GHz. To our knowledge, compared to previously reported W-band mixers, the proposed MHEMT-based resistive mixer using a micromachined ring coupler has shown superior LO–RF isolation and conversion loss.     

Impact of Substrate Digital Noise Coupling on the High-Frequency Noise Performance of RF MOSFETs

The impact of digital noise coupling through the substrate on RF MOSFETs was investigated in terms of the noise figure (NF) of the device up to 26.5 GHz. Previous works on the substrate digital noise coupling have treated the effect mostly in terms of the electrical isolation between ports, rather than actual devices, which does not provide direct information on the degradation of actual device performance parameters from such coupling. In this work, an actual NMOSFET was employed for test and the effect was described in terms of NF, a practical device performance parameter. The results show that NF is significantly degraded as the device enters the weak inversion state and/or $V_{rm ds}$ becomes smaller, suggesting a trade-off between low power operation and immunity against the substrate noise coupling. Also, it is experimentally verified that devices with a dual guard ring showed much smaller NF than those with a single guard ring.      

Low‐Loss Compact Arrayed Waveguide Grating with Spot‐Size Converter Fabricated by a Shadow‐Mask Etching Technique

This paper describes a low‐loss, compact, 40‐channel arrayed waveguide grating (AWG) which utilizes a monolithically integrated spot‐size converter (SSC) for lowering the coupling loss between silica waveguides and standard single‐mode fibers. The SSC is a simple waveguide structure that is tapered in both the vertical and horizontal directions. The vertically tapered structure was realized using a shadow‐mask etching technique. By employing this technique, the fabricated, 40‐channel, 100 GHz‐spaced AWG with silica waveguides of 1.5% relative index‐contrast showed an insertion‐loss figure of 2.8 dB without degrading other optical performance.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Dual‐Transmission‐Line Microstrip Equiripple Lowpass Filter with Sharp Roll‐Off

A novel application of a dual‐transmission line is proposed to design a lowpass filter (LPF). The proposed structure uses only transmission line elements to produce an equiripple LPF response with sharp roll‐off. Design equations are derived using a lossless transmission line model. Controlling the electrical lengths, three transmission‐zeros are realized in the stopband to obtain a sharp roll‐off rate and wide stopband bandwidth. A single unit microstrip LPF with a 3‐dB cut‐off frequency at 1.0 GHz having a roll‐off of 135 dB/GHz along with a stopband bandwidth of 69.5% is designed for validation.     

DC and RF Characteristics of 0.15 pm Power Metamorphic HEMTs

DC and RF characteristics of 0.15 °m GaAs power metamorphic high electron mobility transistors (MHEMT) have been investigated. The 0.15 °m ° 100 °m MHEMT device shows a drain saturation current of 480 mA/mm, an extrinsic transconductance of 830 mS/mm, and a threshold voltage of ‐0.65 V. Uniformities of the threshold voltage and the maximum extrinsic transconductance across a 4‐inch wafer were 8.3% and 5.1%, respectively. The obtained cut‐off frequency and maximum frequency of oscillation are 141 GHz and 243 GHz, respectively. The 8 ° 50 °m MHEMT device shows 33.2% power‐added efficiency, an 18.1 dB power gain, and a 28.2 mW output power. A very low minimum noise figure of 0.79 dB and an associated gain of 10.56 dB at 26 GHz are obtained for the power MHEMT with an indium content of 53% in the InGaAs channel. This excellent noise characteristic is attributed to the drastic reduction of gate resistance by the T‐shaped gate with a wide head and improved device performance. This power MHEMT technology can be used toward 77 GHz band applications.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.