Hysteresis analysis in excimer‐laser‐annealed low‐temperature polycrystalline‐silicon thin‐film transistors

To analyze the hysteresis phenomenon in p‐channel low‐temperature polycrystalline‐silicon thin‐film transistors (LTPS TFTs), the direct correlation between the hysteresis and the interface (N_it) and the grain‐boundary trap density (N_trap) has been investigated. To fabricate LTPS TFTs with different electrical properties and trap types, the thickness of a‐Si was varied from 30 to 80 nm and crystallized by the excimer‐laser‐anneal (ELA) method. The interface trap density is extracted from the subthreshold slope (SS) and low‐high‐frequency C‐V analysis, while the grain‐boundary trap density is extracted by the Levinson and Proano method. The LTPS TFTs with smaller hysteresis exhibited a lower trap density. From the correlation between extracted parameters, the hysteresis seems to be more dependent on N_it and decreases when the film thickness increases to 80 nm while the N_trap is almost the same in all devices.     

Fabrication of low‐temperature‐polysilicon thin‐film transistors on flexible substrates using excimer‐laser crystallization

Abstract— Low‐temperature‐polysilicon thin‐film transistors (LTPS TFTs) were fabricated on polymer substrates using sputtered amorphous‐Si (a‐Si) films and excimer‐laser crystallization. The in‐film argon concentration of a‐Si films was minimized as low as 1.6% by using an argon/helium gas mixture as the sputtering gas. By employing XeCl excimer‐laser crystallization, poly‐Si films were successfully fabricated on polymer substrates with an average grain size of 400 nm. With a four‐mask process, a poly‐Si TFT was fabricated with a fully self‐aligned top‐gate structure, and the pMOS TFT device showed a field‐effect mobility of 63.6 cm²/V‐sec, ON/OFF ratio of 10⁵, and threshold voltage of ?1.5 V.     

Current and future technology of low‐temperature poly‐Si TFT‐LCDs

Abstract— The state of the art of large‐area low‐temperature TFT‐LCDs will be reported in this paper. High‐performance poly‐Si TFTs are expected to realize various applications such as system display where various signal‐processing functions are added to the display. In the past few years, low‐temperature poly‐Si thin‐film‐transistor (LTPS TFT) technology has made great progress, especially in the areas of excimer laser annealing (ELA) of high‐quality poly‐Si film, ion doping for large‐area doping, and high‐quality gate SiO₂ film formation by using the low‐temperature PE‐CVD method. Also, technology trends and possible applications, such as a system displays, will be discussed.     

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Abstract— Low‐temperature polysilicon (LTPS) technology has a tendency towards integrating all circuits on glass substrate. However, the poly‐Si TFTs suffered poor uniformity with large variations in the device characteristics due to a narrow laser process window for producing large‐grained poly‐Si TFTs. The device variation is a serious problem for circuit realization on the LCD panel, so how to design reliable on‐panel circuits is a challenge for system‐on‐panel (SOP) applications. In this work, a 6‐bit R‐string digital‐to‐analog converter (DAC) with gamma correction on glass substrate for TFT‐panel applications is proposed. The proposed circuit, which is composed of a folded R‐string circuit, a segmented digital decoder, and reordering of the decoding circuit, has been designed and fabricated in a 3‐μm LTPS technology. The area of the new proposed DAC circuit is effectively reduced to about one‐sixth compared to that of the conventional circuit for the same LTPS process.     

Comparison of a‐Si and Poly‐Si for AMOLED displays

Abstract— The characteristics of OLED backplanes including the intrinsic properties of a‐Si TFTs and LTPS TFTs will be reviewed. While LTPS TFTs reveal satisfactory stability in AMOLED‐display applications, a‐Si AMOLEDs show better uniformity and are capable of driving OLEDs. However, the stability of a‐Si TFTs under long‐term operation is still unacceptable and remains to be the key issue constraining the commercialization of a‐Si TFT AMOLEDs.     

LTPS circuit integration for system‐on‐glass LCDs

Abstract— A 3.5‐in. QVGA‐formatted driving‐circuit fully integrated LCD has been developed using low‐temperature poly‐Si (LTPS) technology. This display module, in which no external ICs are required, integrates all the driving circuits for a six‐bit RGB digital interface with an LTPS device called a “FASt LDD TFT” and achieves a high‐quality image, narrow frame width, and low power consumption. The LTPS process, device, and circuit technologies developed for system‐on‐glass LCD discussed. The development phase of LTPS circuit integration for system‐on‐glass LCDs is also reviewed.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

High‐efficiency p‐i‐n organic light‐emitting diodes with long lifetime

Abstract— High‐performance organic light‐emitting diodes (OLEDs) are promoting future applications of solid‐state lighting and flat‐panel displays. We demonstrate here that the performance demands for OLEDs are met by the PIN (p‐doped hole‐transport layer/intrinsically conductive emission layer/n‐doped electron‐transport layer) approach. This approach enables high current efficiency, low driving voltage, as well as long OLED lifetimes. Data on very‐high‐efficiency diodes (power efficiencies exceeding 70 lm/W) incorporating a double‐emission layer, comprised of two bipolar layers doped with tris(phenylpyridine)iridium [Ir(ppy)₃], into the PIN architecture are shown. Lifetimes of more than 220,000 hours at a brightness of 150 cd/m² are reported for a red PIN diode. The PIN approach further allows the integration of highly efficient top‐emitting diodes on a wide range of substrates. This is an important factor, especially for display applications where the compatibility of PIN OLEDs with various kinds of substrates is a key advantage. The PIN concept is very compatible with different backplanes, including passive‐matrix substrates as well as active‐matrix substrates on low‐temperature polysilicon (LTPS) or, in particular, amorphous silicon (a‐Si).     

The study of oxide‐interface and grain‐boundary traps in poly‐Si TFT characteristics and its application to fabrication process diagnosis

Abstract— The study of oxide‐interface and grain‐boundary traps in poly‐Si TFT characteristics is reviewed. The subthreshold swing and threshold voltage mainly depend on the density of the oxide‐interface traps (Dit), while the transistor mobility mainly depends on the density of grain‐boundary traps (Dgb). These device properties are applied to diagnose two fabrication processes: plasma treatment and gate‐oxide deposition. It is found that oxygen (O) plasma treatment reduces Dit. This seems to be because O plasma treatment has the ability to terminate the dangling bonds, but O plasma species do not diffuse into the poly‐Si. A model is proposed by comparing the bond energy of the Si‐H and Si‐O‐H. On the other hand, plasma‐enhanced chemical‐vapor deposition (PECVD) of tetraethylorthosilicate (TEOS) for gate oxide increases Dgb. This seems to be because hydrogen (H) plasma species in the TEOS‐PECVD damage the grain boundaries. A model is proposed by considering the reaction processes: hydrolysis, dehydration and bonding, and H plasma species generated during the dehydration.     

Flexible AMOLEDs with low‐temperature‐processed TFT backplane technologies

Developments of backplane technologies, which are one of the challenging topics, toward the realization of flexible active matrix organic light‐emitting diodes (AMOLEDs) are discussed in this paper. Plastic substrates including polyimide are considered as a good candidate for substrates of flexible AMOLEDs. The fabrication process flows based on plastic substrates are explained. Limited by the temperature that plastic substrates can sustain, TFT technologies with maximum processing temperature below 400 °C must be developed. Considering the stringent requirements of AMOLEDs, both oxide thin‐film transistors (TFTs) and ultra‐low‐temperature poly‐silicon TFTs (U‐LTPS TFTs) are investigated. First, oxide TFTs with representative indium gallium zinc oxide channel layer are fabricated on polyimide substrates. The threshold voltage shifts under bias stress and under bending test are small. Thus, a 4.0‐in. flexible AMOLED is demonstrated with indium gallium zinc oxide TFTs, showing good panel performance and flexibility. Further, the oxide TFTs based on indium tin zinc oxide channel layer with high mobility and good stability are discussed. The mobility can be higher than 20 cm²/Vs, and threshold voltage shifts under both voltage stress and current stress are almost negligible, proving the potential of oxide TFT technology. On the other hand, the U‐LTPS TFTs are also developed. It is confirmed that dehydrogenation and dopant activation can be effectively performed at a temperature within 400 °C. The performance of U‐LTPS TFTs on polyimide is compatible to those of TFTs on glass. Also, the performance of devices on polyimide can be kept intact after devices de‐bonded from glass carrier. Finally, a 4.3‐in. flexible AMOLED is also demonstrated with U‐LTPS TFTs.     

PECVD films for low‐temperature poly‐Si TFT‐LCD applications

Low‐temperature polycrystalline‐silicon (poly‐Si) thin‐film‐transistor (TFT) processes, based on PECVD amorphous‐silicon (a‐Si:H) precursor films and excimer‐laser crystallization, have been developed for application in the fabrication of active‐matrix liquid‐crystal‐displays (AMLCDs). The optimum process for depositing the precursor films has been identified. The relationship between excimer‐laser crystallization and poly‐Si film morphology has also been studied. Using these techniques, poly‐Si TFTs with a mobility of 275 cm²/V‐sec and on/off ratios of 1 × 10⁷ have been fabricated.     

Fabrication of poly‐Si complementary metal oxide semiconductor inverter by all sputtering deposition process

Direct current sputtering was used for deposition of Si film for precursor film of excimer laser annealing, n⁺‐Si/p⁺‐Si film for source/drain contact, and SiO₂ film for gate insulator of polycrystalline silicon thin‐film transistor. Using these methods, poly‐Si thin‐film complementary metal oxide semiconductor inverter was fabricated by all sputtering process for the first time. The field‐effect mobility was, respectively, 6.5 and 12.5 cm²/Vs for n‐TFTs and p‐TFTs. This inverter exhibits a full rail‐to‐rail swing and abrupt voltage transfer characteristics over the entire voltage range, and the output voltage gain was ~117 at V_dd = 20 V.     

Silicon‐nanocrystal‐based photosensor integrated on low‐temperature polysilicon panels

Abstract— A photodetector using a silicon‐nanocrystal layer sandwiched between two electrodes is proposed and demonstrated on a glass substrate fabricated by low‐temperature poly‐silicon (LTPS) technology. Through post excimer‐laser annealing (ELA) of silicon‐rich oxide films, silicon nanocrystals formed between the bottom metal and top indium thin oxide (ITO) layers exhibit good uniformity, reliable optical response, and tunable absorption spectrum. Due to the quantum confinement effect leading to enhanced phonon‐assisted excitation, these silicon nanocrystals, less than 10 nm in diameter, promote electron‐hole‐pair generation in the photo‐sensing region as a result resembling a direct‐gap transition. The desired optical absorption spectrum can be obtained by determining the thickness and silicon concentration of the deposited silicon‐rich oxide films as well as the power of post laser annealing. In addition to obtaining a photosensitivity comparable to that of the p‐i‐n photodiode currently used in LTPS technology, the silicon‐nanocrystal‐based photosensor provides an effective backlight shielding by the bottom electrode made of molybdenum (Mo). Having a higher temperature tolerance for both the dark current and optical responsibility and maximizing the photosensing area in a pixel circuit by adopting a stack structure, this novel photosensor can be a promising candidate for realizing an optical touch function on a LTPS panel.     

Optimization of low‐temperature poly‐Si TFT‐LCDs and a large‐scale production line for large glass substrates

Abstract— An update of the progress of inherently low‐temperature poly‐Si (LTPS) technologies, such as ELA, ion doping, and activation in conjunction with chemical vapor deposition (CVD) and photolithography will be given. We will also discuss whether LTPS LCDs will be applied to a large‐scale production line using a large motherglass substrate. It was found that a more‐powerful excimer laser as well as photolithography with higher‐resolution and a more‐precise overlaid arrangement would enable a large‐scale production line handling motherglass of 4th generation size to be constructed in the very near future with reasonable investment and productivity costs.     

Novel LTPS technology for large substrate

We developed partial laser anneal silicon (PLAS) thin‐film transistor (TFT) of novel low‐temperature polycrystalline‐silicon (LTPS) technology, which had the mobility of 28.1 cm²/Vs lager than that of mass produced oxide TFT and photo‐stability comparable with that of LTPS TFT in bottom gate structure. This innovative technology enables the conversion from an α‐Si TFT to a high‐mobility TFT most easily and inexpensively. Moreover, there is no limit of substrate size, such as Gen10 and more. Photo‐stability of PLAS will be suitable to organic light‐emitting diode backplane, high‐dynamic range TV, and outdoor IDP.     

Characterization of a SAG‐InGaN/AlGaN LED by mixed‐source HVPE with a multi‐sliding boat system

Abstract— The selective area growth (SAG) of a InGaN/AlGaN light‐emitting diode (LED) is performed by using mixed‐source hydride vapor‐phase epitaxy (HVPE) with a multi‐sliding boat system. The SAG‐InGaN/AlGaN LED consists of a Si‐doped AlGaN cladding layer, an InGaN active layer, a Mg‐doped AlGaN cladding layer, and a Mg‐doped GaN capping layer. The carrier concentration of the n‐type Al_xGa_1?xN (x ～ 16%) cladding layer depends on the amount of poly‐Si placed in the Al‐Ga source. The carrier concentration is varied from 2.0 × 10¹⁶ to 1.1 × 10¹⁷ cm^?3. Electroluminescence (EL) characteristics show an emission peak wavelength at 426 nm with a full width at half‐maximum (FWHM) of approximately 0.47 eV at 20 mA. It was found that the mixed‐source HVPE method with a multi‐sliding boat system is a candidate growth method for III‐nitride LEDs.     

Development of rapid thermal processor for large‐glass LTPS production

Abstract— A field‐enhanced rapid‐thermal‐processor (FE‐RTP) system that enables LTPS LCD and AMOLED manufacturers to produce poly‐Si films at low cost, high throughput, and high yield has been developed. The FE‐RTP allows for diverse process options including crystallization, thermal oxidation of gate oxides, and fast pre‐compactions. The process and equipment compatibility with a‐Si TFT manufacturing lines provides a viable solution to produce poly‐Si TFTs using a‐Si TFT lines.     

Active‐matrix OLED backplanes based on LTPS for small molecules and polymers

Abstract— A four‐mask low‐temperature poly‐Si (LTPS) TFT process for p‐ and n‐channel devices has been developed. PECVD‐deposited amorphous silicon was recrystallized to polycrystalline‐silicon with single‐area excimer‐laser crystallization, while the gate dielectric was fabricated by PECVD deposition of a SiH₄‐N₂O‐based silicon oxide. Formation of drain and source was carried out with self‐aligned ion‐beam implantation. To prove the potential capability of these devices, which are suitable for conventional and inverted OLEDs alike, several functional active‐matrix backplanes implementing different pixel circuits have been produced. This active‐matrix backplane process has been customized to drive small molecules as well as polymers regardless if its structure is top or bottom emitting.     

Effects of post‐annealing on a‐Si:H TFT characteristics fabricated on stainless‐steel substrate

Abstract— A 14.1‐in.‐diagonal backplane employing hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) was fabricated on a flexible stainless‐steel substrate. The TFTs exhibited a field‐effect mobility of 0.54 cm²/V‐sec, a threshold voltage of 1.0 V, and an off‐current of 10^?13 A. Most of the electrical characteristics were comparable to those of the TFTs fabricated on glass substrates. To increase the stability of a‐Si:H TFTs fabricated on stainless‐steel substrate, the specimens were thermally annealed at 230°C. The field‐effect mobility was reduced to 71% of the initial value because of the strain of the released hydrogen atoms and residual compressive stress in a‐Si:H TFT under thermal annealing at 230°C.     

Process study and optimization for fabrication of poly‐Si thin‐film transistors on plastic substrates

Abstract— A complete poly‐Si thin‐film transistor (TFT) on plastic process has been optimized to produce TFT arrays for active‐matrix displays. We present a detailed study of the poly‐Si crystallization process, a mechanism for protecting the plastic substrate from the pulsed laser used to crystallize the silicon, and a high‐performance low‐temperature gate dielectric film. Poly‐Si grain sizes and the corresponding TFT performance have been measured for a range of excimer‐laser crystallization fluences near the full‐melt threshold, allowing optimization of the laser‐crystallization process. A Bragg reflector stack has been embedded in the plastic coating layers; its effectiveness in protecting the plastic from the excimer‐laser pulse is described. Finally, we describe a plasma pre‐oxidation step, which has been added to a low‐temperature (<100°C) gate dielectric film deposition process to dramatically improve the electrical properties of the gate dielectric. These processes have been integrated into a complete poly‐Si TFT on plastic fabrication process, which produces PMOS TFTs with mobilities of 66 cm² /V‐sec, threshold voltages of ?3.5 V, and off currents of approximately 1 pA per micron of gate width.