Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation

Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a different decoder design approach that is specifically intended for an FPGA implementation. We reformulate the mixed-domain FFT-BP decoding algorithm and develop a decoder architecture that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA, thus making use of all the types of FPGA resources. Then, the throughput limit achievable in a single FPGA by the proposed decoder is significantly increased. We also consider another important optimization of the decoder implementation, mainly an efficient realization of the permutation units and an approximated evaluation of the nonlinear functions of messages. Another motivation is to make the decoder easily scalable for FPGA devices of different sizes. To achieve this goal, the configurable semi-parallel decoder architecture is applied operating for the structured subclass of codes.     

Design for Testability of CMOS Analog Sum-Product Error-Control Decoders

A built-in self-test (BIST) technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation.     

Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders

By optimizing the number of look-ahead steps of the first layer of the previous low-latency architectures for M-step look-ahead high-throughput rate Viterbi decoders, this paper improves the hardware efficiency by large percentage with slight increase or even further decrease of the latency for the add-compare-select (ACS) computation. This is true especially when the encoder constraint length (K) is large. For example, when ${rm K}=7$ and M varies from 21 to 84, 20.83% to 41.27% of the hardware cost in previous low latency Viterbi method can be saved with only up to 12% increase or 4% decrease of the latency of the conventional M-step look-ahead viterbi decoder. The proposed architecture also relaxes the constraint on the look-ahead level M to be a multiple of K as was needed in the previous work. For example, when ${rm K}=7$ and M (indivisible by K) varies from 40 to 80, 60.27% to 69.3% latency of conventional M-step look ahead Viterbi architecture can be reduced at the expense of 148.62% to 320.20% extra hardware complexity.      

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

GaAs超高速模拟开关集成电路

本文首次报导了GaAs超高速模拟开关集成电路的设计、制备及主要结果。已制备出开启时间最好水平为0.7ns的实用开关集成电路是目前速度最快的模拟开关集成电路。     

Equipment Throughput Optimization by Means of Speed Loss Analysis

Consistent with the Semiconductor Industry's focus on continuous improvement, increased throughput, and shorter cycle times, this paper describes a methodology for the qualification and quantification of speed loss at a toolset level. The identification and quantification of the speed loss categories, along with implementation of specific actions targeted at these losses, has enabled our fab to have a direct impact on overall capacity and throughput performance of our toolsets.      

一种单刀双掷高速模拟开关的研制

介绍了一种单刀双掷高速模拟开关;描述了电路工作原理、线路设计、版图设计及可靠性设计。该高速模拟开关具有速度快、功耗低、隔离度高、关断漏电流小等特点。其内部电路设计有控制输入级、电平转换级、高速模拟开关管及静电保护电路。该电路可广泛应用于雷达接收机和发射机、通信系统和数据采集系统,以及通用模拟开关等领域。     

System Parameters and Performance of High Speed Modems on Analog Radio

High speed modems are a means for implementing early 100 percent digital connectivity in the transition to total digital networks. The system parameters for high speed data transmission over FM and SSB microwave radio are calculated. It is shown that radio fading is not necessarily a controlling factor. Other impairments such as noise, level, and phase transients are experienced on long terrestrial circuits. The setup for field measurements and results are presented. Technical and economic network criteria are presented that led to the decision to deploy 1.544 Mbit/s modems on analog microwave radio.     

Analog Viterbi Decoding for High Speed Digital Satellite Channels

Analog means for implementing the Viterbi decoding algorithm at high data rates are presented. One approach employs sample-and-hold circuits and voltage adders to store and update the path metrics based upon maximum-likelihood decisions. Experimental results obtained from a breadboard realization of such a decoder are reported. An alternate approach employing tapped delay lines to store the analog channel waveform is also described. Analytical results pertaining to each implementation are presented.     

PLC模拟量控制在变频调速的应用

本文以三菱PLC为例介绍了模拟量控制，并结合变频调速基本原理及特点，重点阐述了如何通过PLC模拟量控制来实现对变频器的速度调节。     

用于超便携式和消费电子设备USB2.0的模拟开关

由于PC主机与便携式设备如手机之间所需的数据吞吐量不断增大,USB 2.0高速I/O(480Mbps)在便携式应用领域的使用日益增多.在功能性的需求带动下,外设设备控制器或基带处理器需要接入USB端口,以便与外部PC主机进行通信.     

应用于数字和模拟光通信的高速电吸收光调制器

An electro-absorption （EA） modulator is one of key components for optical fiber communications due to the high speed, small size, low voltage and integration ability with other semiconductor devices. A 40 Gb/s InGaAsP/InP multiple-quantum-well （MQW） EA modulator monolithically integrated with a semiconductor optical amplifier （SOA） was fabricated for digital communications. The modulator capacitance was reduced to obtain 40 GHz bandwidth, and the SOA section helped reduce the insertion loss from 18 dB to 3 dB. InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications. A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz^2/3 were estimated by static and dynamic measurements.     

一种具有快速收敛特性的盲自适应波束形成算法

本文提出了一种基于信号的周期平稳特性的具有快速收敛特性的盲波束形成新方法。该盲算法应用了ＲＬＳ技术,仿真实验证明该算法的收敛速度快于Ｃａｓｔｅｄｏ 等人提出的随机梯度算法     

一种高速宽带BJT模拟开关的设计与实现

本文采用射极跟随器、电流镜、非饱和电流开关等高速单元电路设计了一种新颖的BJT模拟开关.它具有速度快,频带宽,隔离度高,动态范围大,线性好等优点.介绍了电路结构,分析了电路的工作原理,给出了电路性能的仿真结果和芯片电路指标测试结果,并总结了电路的主要特点.所设计的电路可以做成单片集成电路,也可以作为一个基本单元应用于大规模集成芯片中.     

Generic Description and Synthesis of LDPC Decoders

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.     

Parallel Scalability of Video Decoders

An important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs) are expected to contain. As a case study we investigate the parallelism available in video decoders, an important application domain now and in the future. Specifically, we analyze the parallel scalability of the H.264 decoding process. First we discuss the data structures and dependencies of H.264 and show what types of parallelism it allows to be exploited. We also show that previously proposed parallelization strategies such as slice-level, frame-level, and intra-frame macroblock (MB) level parallelism, are not sufficiently scalable. Based on the observation that inter-frame dependencies have a limited spatial range we propose a new parallelization strategy, called Dynamic 3D-Wave. It allows certain MBs of consecutive frames to be decoded in parallel. Using this new strategy we analyze the limits to the available MB-level parallelism in H.264. Using real movie sequences we find a maximum MB parallelism ranging from 4000 to 7000. We also perform a case study to assess the practical value and possibilities of a highly parallelized H.264 application. The results show that H.264 exhibits sufficient parallelism to efficiently exploit the capabilities of future manycore CMPs.

一种快速公平收敛的拥塞控制算法

 传统的拥塞控制算法在网络容量或往返延时很大时表现出很低的平衡收敛速度.本文提出一种称之为NMKC的算法改善公平收敛速度.算法基于网络反馈进行模式切换:低负载模式采用MKC的源端控制方程调整发送速率,从而指数收敛到效率;高负载模式构建了一种新颖的源端更新方法提高公平收敛速度.理论证明了新方法的稳定性和收敛性能,NS仿真实验表明新方法能显著提高公平收敛速度.     

Analog and Digital Speed Control of DC Drives Using Proportional-Integral and Integral-Proportional Control Techniques

A comparative study of proportional-integral (P-I) and integral-proportional (I-P) control schemes, for the speed control of a dc drive, using both analog-and microprocessor-based digital circuits, is presented. The often-neglected current response is discussed and results are presented. The speed response to step changes in speed reference and load torque, using both the control schemes, is compared to evaluate the merits of I-P control. A brief discussion of sensitivity to controller gains is also given. It is shown that the I-P control scheme offers some distinctive advantages over P-I control. Experimental and simulation results are also presented.     

Viterbi译码器的优化设计

Ｖｉｔｅｒｂｉ译码器中的大容量、宽带宽存储器限制了译码器的速度和系统的功耗,合理地组织这个存储器是提高译码器速度,降低系统功耗的关键。从电路系统角度分析了Ｖｉｔｅｒｂｉ译码器的结构,提出了一种优化设计方案。     

Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity

A digital CMOS buffer circuit with avoltage transfer characteristic (VTC) with lowthreshold voltage detection, hysteresis, andhigh noise immunity is presented. The circuitis capable of restoring slow transition timesand distorted input signals with a minimumdelay penalty, offering at the same time highnoise immunity to glitches induced eitherthrough capacitive coupling or from the powersupply lines. The high noise immunity of theproposed buffer circuit is achieved usingdifferential mode rejection and a differentialredundant circuit architecture.