Micropower high current‐drive class AB CMOS current‐feedback operational amplifier

A novel CMOS current‐feedback operational amplifier (CFOA) aimed to low‐power applications is proposed. The use of a compact class AB implementation allows high current‐drive capability and simultaneously very low quiescent power consumption. Measurement results of a fabricated prototype show for an inverting configuration a closed‐loop bandwidth of 1 MHz independent of gain setting, and a slew rate of 2V/µs for a load capacitance of 30 pF and a quiescent power consumption of 264µW. Copyright © 2010 John Wiley & Sons, Ltd.     

CMOS专用电路电磁发射测量和电磁兼容性预测模型

文章介绍测量CMOS大规模集成电路电磁发射的方法；辐射方式TEM法和传导方式VDE法。提出了集成电路级传导电磁发射模型，模型计及测试接口、布局图连接线、电路封装、动态电流源及IC寄生参数等方面的影响。模型的建立，采用软件分析和实验测量相结合的方法。模型可以方便地置入常用的模拟分析器，在IC设计阶段，对10－1000MHz电路的电磁兼容特性进行预测。     

Phase noise analysis in CMOS differential Armstrong oscillator topology

This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano‐scale CMOS LC oscillators. Copyright © 2016 John Wiley & Sons, Ltd.     

A high-resolution all-digital pulse-width modulator architecture with a tunable delay element in CMOS

A design for an all-digital high-resolution pulse-width modulator (HRPWM) architecture is presented in this work. The architecture is based on a novel digitally controlled delay element that combines two different approaches, achieving a variable time interval up to 54 ps, and adjustable against process, voltage, and temperature (PVT) variations. The proposed system uses several delay elements with a counter-based digital pulse-width modulator (DPWM) in a hybrid configuration, which allows to obtain duty cycles with 18-bit resolution without using a high-frequency internal clock and maintaining a low power dissipation. The HRPWM was implemented in a standard low-cost 130-nm CMOS technology, together with a memory used to store the duty cycles, and a serial communication module. Post layout simulation results show good linearity between the control word and the duty cycle in all the range. The chip can be fine tuned to improve its performance using the calibration capabilities of the architecture. The analysis includes a comparison with another state-of-art HRPWMs showing the advantages of the proposed approach.     

Analysis of parasitic quantum effects in classical CMOS circuits

In the mesoscopic regime, the MOS device performance is affected by gate‐induced quantization effects leading to a loss of transconductance and threshold voltage shift and gate leakage tunnelling currents degrading the overall device performance. We discuss the expected impact of quantum effects in highly down scaled CMOS circuits. Based on 1‐d numerical simulations for transport in mesoscopic systems, we set up Spice circuit models. The Spice models rebuild the influence of quantum effects; and the functionality of classical circuit concepts can be ‘tested’ in their robustness against these effects. A few circuit examples will be given. Copyright © 2005 John Wiley & Sons, Ltd.     

Analytical comparison of frequency compensation techniques in three‐stage amplifiers

In this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade‐off between gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small‐signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright © 2006 John Wiley & Sons, Ltd.     

CMOS模拟开关在自整角机信号处理中的应用

采用分时复用技术设计伺服系统的架位信号反馈电路,以达到化简电路、节约设备成本的目的。但该目的的实现,关键在于能否找到用集成CMOS模拟开关来切换幅值高达百伏以上的自整角机信号的技术。通过对电路环境的分析,给出了解决这该问题的思路和技术实现的过程,并给出了电路设计时的相关要点。     

900 MHZ radio‐frequency identification rectifier with optimization and reusing of electro‐static discharges protections in 180 nm digital CMOS technology

Sensitivity and electro‐static discharges (ESD) protection level are crucial parameters for any Ultra High‐Frequency (UHF) power rectifier–harvester designed for radio‐frequency identification (RFID) devices. While sensitivity limits the reading range of the interrogator‐to‐tag communication link, the requirement for an adequate protection against ESD is enforced in commercial devices connected to a printed antenna. Both resistive and capacitive parasitics of the protection circuits severely affect RF performance of the device. In the paper, a rectifier for UHF RFID embedding an ESD protection for 2 kV human‐body discharge model (HBM) level is proposed. The target of a low added parasitic capacitance is achieved by adapting the protection circuit to the RFID rectifier and reusing the ESD clamp for additional functions being mandatory in a UHF RFID front end. The layout of the ESD clamp has been optimized for minimum parasitic resistance without sacrificing the protection level. Two UHF harvesters were implemented in a 180 nm digital complementary metal‐oxide semiconductor (CMOS) technology, featuring a minimum sensitivity of ?15.5 dBm with an ESD protection level of 2 kV HBM. Copyright © 2014 John Wiley & Sons, Ltd.     

Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band

This paper presents a design of a CMOS cross-coupled voltage-controlled oscillator (VCO) using active inductors (AIs) for wide-band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator-C topology as the basic structure to generate an inductance. The VCO uses a cross-coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65-nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1-MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm² including the pads. The proposed AI-VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.     

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

On the input common‐mode voltage range of CMOS bulk‐driven input stages

In this paper the response of a bulk‐driven MOS Metal‐Oxide‐Semiconductor input stage over the input common‐mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35‐µm CMOS Complementary Metal‐Oxide‐Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source‐bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk‐driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5‐V second‐order operational transconductance amplifier (OTA)‐C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright © 2010 John Wiley & Sons, Ltd.     

混合电动车用的功率模块在使用新技术后的功率循环性能

本文给出了联合研究项目"用于主变速器的电气部件"的一些研究结果。电力电子的冷却是由发动机的冷却电路来实现的。发动机的温度可以达到105℃,在极端情况下,可以达到125℃。因此,功率器件必须经受高于200℃的温度。其面对的挑战是功率循环周期的能力。通过改进封装技术,可以实现该要求。本文进行了系统的功率循环测试,说明了不同的失效模式,并对改进的性能做了评价。结果表明:采用新技术,使得功率循环寿命因子提高到100。     

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S‐parameter measurements in silicon. These S‐parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.7 V, 2.7 μW, 12.9 ppm/° C over 180° C CMOS subthreshold voltage reference

An all‐CMOS, low‐power, wide‐temperature‐range, curvature‐compensated voltage reference is presented. The proposed topology achieves a measured temperature coefficient of 12.9 ppm/°C for a wide temperature range of 180°C ( − 60 to 120°C) at a bias voltage of 0.7 V while consuming a mere 2.7 μW. The high‐order curvature compensation, which leads to a low‐temperature sensitivity of the reference voltage, is performed using a new, simple, but efficient methodology. The non‐linearities of an N‐type metal‐oxide‐semiconductor (NMOS) device operated in subthreshold are combined with the non‐linearities of two different kinds of polysilicon resistors, leading to the improved performance. The extended temperature range of this voltage reference gives it an important competitive advantage, especially at lower temperatures, where prior art designs' performance deteriorate abruptly. In addition, it utilizes an innovative trimming methodology whereby two trimmable resistors enable the tuning of both the overall slope and non‐linearities of the temperature sensitivity. The design was fabricated using TowerJazz Semiconductor's CMOS 0.18 μm technology, without using diodes or any external components such as compensating capacitors. It has an area of 0.023 mm² and is suitable for high‐performance power‐aware applications as well as applications operating in extreme temperatures. Copyright © 2016 John Wiley & Sons, Ltd.     

Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

This paper uses a CAD methodology proposed by the authors to design a low-power second-order ΣΔM. This modulator has been fabricated in a 0·7 μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16·4 bit at a digital output rate of 9·6 kHz with a power consumption of 1·71 mW. It yields a value of the power(W)/(2^{Resolution(bit)}×output rate (Hz)) figure which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. © 1997 by John Wiley & Sons, Ltd.