共查询到16条相似文献,搜索用时 93 毫秒
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同步设计中,由于时钟网络延时决定了芯片的最大工作速度,所以时钟树需要高精度进行布线。一种重要的时钟网络设计是缓冲器插入。在超大规模集成电路的设计中,为了最小化时钟延时和时钟偏差,缓冲器插入是一种有效的方法。在布局布线流程中,时钟树布线在“时钟树综合”时由工具自动完成。“时钟树综合”在apollo里是在布局完成后布线之前做的。 相似文献
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时钟延时及偏差最小化的缓冲器插入新算法 总被引:2,自引:0,他引:2
本文提出了以最小时钟延时和时钟偏差为目标的缓冲器插入新算法.基于Elmore延时模型,我们得到相邻缓冲器间的延时是缓冲器在时钟树中位置的凸函数.当缓冲器布局使所有缓冲器间延时函数具有相同导数值时,时钟延时达到最小;当所有源到各接收端点路径的延时函数值相等时,时钟偏差达到最小.对一棵给定的时钟树,我们在所有从源点到各接收端点路径上插入相同层数的缓冲器,通过优化缓冲器的位置实现时钟延时最小;通过调整缓冲器尺寸和增加缓冲器层数,实现时钟偏差最小. 相似文献
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为了在基于TSV的3D-IC中实现成本效率高的时钟树布线,介绍一个3D时钟树综合算法.对于一个给定抽象时钟树的拓扑结构,给出了一个3D时钟树嵌入算法来最小化TSV个数。如果没有给定抽象树拓扑结构,提出了一个NN-3D算法来生成抽象树.最后,插入缓冲器来进一步降低时钟树的延时以及最大负载电容.这几个步骤连接起来就形成一个完整的时钟树综合算法.通过Matlab建模验证,这个算法在布线总长度、延时、功耗以及TSV个数等各方面综合考量下获得了很好的效果,进一步降低了3D-IC的成本以及功耗散热问题. 相似文献
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Qing Zhu Wayne Wei-Ming Dai 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1996,4(2):210-226
A new concept of chip and package co-design for the clock network is presented in this paper. We propose a two level clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster. The clock signal is then distributed from the main clock driver to each of local buffers by means of a global clock tree, which is a planar tree with equal path lengths. With the flip chip area I/O attachment, the planar global clock tree can be put on a dedicated package layer. The interconnect on the package layer has two to four order smaller resistance than that on the chip layer. The main contribution of this paper is a novel algorithm to construct a planar clock tree with equal path lengths-the length of the path from the clock source to each destination is exactly the same. In addition, the path length from the source to destinations is minimized 相似文献
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Chia-Chun TsaiAuthor Vitae Chung-Chieh KuoAuthor VitaeFeng-Tzu HsuAuthor Vitae Trong-Yen LeeAuthor Vitae 《Integration, the VLSI Journal》2012,45(1):76-90
Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n2) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree. 相似文献
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Nan-Chi Chou Chung-Kuan Cheng 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1995,3(1):141-146
We propose a simulated annealing based zero-skew clock net construction algorithm that works in any routing spaces, from Manhattan to Euclidean, with the added flexibility of optimizing either the wire length or the propagation delay. We first devise an O(log n) tree grafting perturbation function to construct a zero-skew clock tree under the Elmore delay model. This tree grafting scheme is able to explore the entire solution space asymptotically. A Gauss-Seidel iteration procedure is then applied to optimize the Steiner point positions. Experimental results have shown that our algorithm can achieve substantial delay reduction and encouraging wire length minimization compared to previous works 相似文献
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本文以sha256算法模块的数字后端物理设计为例,提出了将多时钟源分割技术应用在传统时钟树综合中的方法。应用该方法后,利用有效时钟偏移,仅通过少量时钟缓冲器的插入就解决了该模块设计中的建立时间违例问题,大大降低了后续时序收敛工作的复杂度,将时序修复耗时缩短为采用传统方法的20%。 相似文献